Functional Description; Hardware; Input Reference Signals - Symmetricom TSG-3800 Series User Manual

Subtending Operating Mode

Functional Description

Functional Description
The TSG-3800 is designed in accordance with the Building Integrated Timing
Supply (BITS) concept for intraoffice synchronization distribution. The BITS concept
provides a synchronization hierarchy that is traceable back to one master clock
(TSG), or redundant master clock pairs, referred to as the BITS. The BITS provides
DS1 and Composite Clock (CC) timing to all synchronized clocks in the office, which
provides timing inputs for all remote (subtending) TSGs.
The TSG-3800 configured as a Subtending TSG provides remote phase
synchronization and holdover capabilities to telecom network elements, such as
digital switches, Digital Access Crossover Systems (DACS), and channel banks for
customers with very large equipment offices. For further information on Subtending
TSGs, refer to Section 7 of Telcordia Specification GR-378-CORE.

Hardware

The 3800 Subtending TSG is used when there is a need for more timing outputs
than can be supplied by a single TSG. The 3800 Subtending TSG receives
redundant Composite Clock (CC) and DS1 reference signals directly from the
Master BITS Clock. The CC signals are used for primary and secondary inputs and
the 3800 phase locks to the selected reference to ensure proper DS0 phase
alignment throughout the office. The redundant DS1 reference inputs are used only
for Clock Bypass operation. If both CC reference inputs fail, the shelf provides
Stratum 3E holdover stability. If both CC reference inputs fail and both 3E Clock
modules fail the 3800 Subtending TSG uses the DS1 reference inputs for clock
bypass operation

Input Reference Signals

The 3800 Subtending TSG configuration requires two composite clock and two DS1
reference input signals. The CC inputs are used as the reference signals and the
DS1 inputs are used for Clock Bypass signals only. In the 3800 Subtending TSG
configuration, the DS1 inputs are connected to T1 and R1 of inputs 1.1 and 2.1. The
1-Port DS1 Input modules (P/N 23478303-002-0) located in slots 1 and 2 provide
monitoring and termination capability of the DS1 bypass signals. The Composite
Clock input signals are connected to T1 and R1 of inputs 3.1 and 4.1 and are
internally terminated. Switching references can occur repeatedly without
accumulating phase or frequency error. The operator can manually or automatically
select the reference. Restoring the primary reference source can return the 3800 to
tracking the primary signal. Refer to Modules, on page 298, for a list of the output
modules supported by this configuration.
296 TSG-3800 User's Guide
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12778474-002-2 Revision F – March 2004