Block Diagram Of The Clock Module - Symmetricom TSG-3800 Series User Manual

CPU, Frame Generator, and Clock Modules
Clock Module
Figure 6-5.

Block Diagram of the Clock Module

The Direct Digital Synthesizer receives a digital control value from the module
control circuits. It then uses this value to generate a precise 16 kHz frequency from
the Numeric Controlled Oscillator (NCO) and associated Digital to Analog Converter
(DAC) and filter circuit. The digital Control Value (CV) is a 48-bit word that provides
adjustment of the output frequencies in steps of approximately 2.2 parts in 10
the required tuning range.
The Timing Circuitry consists of a phase locked loop (PLL) using a voltage
controlled crystal oscillator (VCXO) to produce an 18.528 MHz output signal and a
divider to produce a one pulse per second (1PPS) timing signal. Included in the
timing circuits is provision to allow synchronization of these outputs between
redundant modules through CPU control. These output signals go to all Input
modules to be used for measurement of the input signals, and to the associated
Frame Generator module for generating the output signals.
The Module Control section includes the address and data buffers to communicate
with the CPU module via the system backplane and the CV memory and status
registers to control operation. This section also operates the front panel indicators to
show the status of the module. A watchdog timer is included which will automatically
switch the module into Holdover mode of operation if the CV is not updated by the
CPU each second.
180 TSG-3800 User's Guide
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