Configuring The Cpu Module - Symmetricom TSG-3800 Series User Manual

Timing signal generator
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Table 6-3. EIA-232 Communications Pinout Specifications
DTE
PIN
FUNCTION
1
Chassis
Ground
2*
TXD
3*
RXD
4
RTS
5
CTS
6
DSR
7*
Signal
Ground
8
DCD
20
DTR
NOTE: Pins 9–19, and 21–25 are not used. * Denotes minimum connections necessary. See
Section 3 for use of control lines. Avoid connecting pins 1 and 7 together if signal ground and
chassis ground are isolated in installation.

Configuring the CPU Module

Caution: To prevent ESD damage to the module, always observe
the precautions described in
page 61.
Before connecting a peripheral device, be sure to set the baud rate. The default
baud rate is 9600. The EIA-232 port uses 8-bit, no parity, 1 stop bit character
framing.
Connections for COMM A and COMM B may be set independently for
communicating with different devices (COMM A to a PC and COMM B to a modem).
You must configure a set of jumpers for each EIA-232 port for use with the desired
device. The jumper positions for COMM A and COMM B are identical if you are
using the same type of device for both ports. Refer to
12778474-002-2 Revision F – March 2004
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CPU, Frame Generator, and Clock Modules
PIN
1
2*
3*
4
5
6
7*
8
20
Properly Handling the
Modules, on
Table 6-4
CPU Module
DCE
FUNCTION
Chassis
Ground
TXD
RXD
RTS
CTS
DSR
Signal
Ground
DCD
DTR
for jumper positions.
TSG-3800 User's Guide 175

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