Timer Status Registers; Porta Configuration Register - Digi NS7520B-1-C36 Hardware Reference Manual

Timer Status registers

Address: FFB0 0014 / FFB0 001C
31 30
Rsvd TIP
15 14
Register bit assignment
Bits
D31
D30
D29:27
D26:00
Table 28: Timer Status registers bit definition

PORTA Configuration register

Address: FFB0 0020
29 28 27 26
Reserved TCLK
13 12 11 10
Access Mnemonic Reset
N/A Reserved N/A
R/C TIP 0
N/A Reserved N/A
R CTC O
25 24 23 22 21
CTC
9 8 7 6 5
CTC
Description
N/A
Timer interrupt pending
Set to 1 when the timer is enabled and the CTC value
counts down to 0. TIP generates an interrupt to the CPU if
the TIE bit in the Timer Control register is set. Writing a 1
to the same bit position in the Timer Status register clears
the TIP bit.
Note: TIP is set immediately when the TE bit (in the
Timer Control register) is changed from 0 to 1.
An interrupt occurs immediately after TE
transitions from 0 to 1. If this initial interrupt
causes a problem in any specific application, the
software must be designed to ignore the first
interrupt after TE transitions from 0 to 1.
N/A
Current timer count
Each time the CTC field reaches zero, the TIP bit is set and
the CTC is reloaded with the value defined in the ITC field.
The CTC continues to count back down to zero.
w w w . d i g i e m b e d d e d . c o m
G E N M o d u l e
20 19 18 17 16
4 3 2 1 0
7 3