Digi NS7520B-1-C36 Hardware Reference Manual page 298

T i m i n g D i a g r a m s
FP DRAM write
Fast Page write
TA* (Note-4)
TEA*/LAST (Note-4)
Non-muxed address
Muxed address
write D[31:0]
(FP)RAS[4:0]*
(FP)CAS[3:0]*
PortA2/AMUX
Notes:
If the next transfer is DMA, null periods between memory transfers can occur.
1
Thirteen clock pulses are required for DMA context switching.
Port size determines which byte enable signals are active:
2
–
–
–
Port size determines which CAS signals are active:
3
–
–
–
The TA* and TEA*/LAST signals are for reference only.
4
2 8 6
T1
BCLK
TA* (input)
36
Note-2
BE[3:0]*
6
35
WE*
Note-3
12
RW*
8-bit port = BE3*
16-bit port = BE[3:2]
32-bit port = BE[3:0]
8-bit port = CAS3*
16-bit port = CAS[3:2]
32-bit port = CAS[3:0]
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
TW T2
30
31
14
9
29
27
43
37
Note-1 T1
30
31
15
36
13
29
27
43
37