Chip Select Base Address Register - Digi NS7520B-1-C36 Hardware Reference Manual

M E M m o d u l e c o n f i g u r a t i o n
Bits
D16
D15:00
Table 36: MMCR bit definition
A27 and A26 bit settings
The A27 bit setting determines how the A27 signal is used by the NS7520. CS0OE_ is
generated by an internal logical AND of the CS0_ and OE_ signals. The CS0OE_ signal
goes active low when both CS0_ and OE_ are active low.
The A26 bit setting determines how the A26 signal is used by the NS7520. The CS0WE_
signal is generated by an internal logical AND of the CS0_ and WE_ signals. the
CS0WE_ signal goes active low when both CS0_ and WE_ are active low.
When enabled, these signals maximize the read access timing for external memory
peripherals attached to CS0. When using CS0OE_, the CS0 peripheral's chip select
input is attached to GND, and the read-access time for that peripheral is referenced
from address instead of chip select. The NS7520 provides the address signals during
the earliest part of each memory cycle. The CS0OE_ and CS0WE_ signals are
connected to the OE_ and WE_ input for the CS0 peripheral.

Chip Select Base Address register

Address: FFC0 0010/20/30/40/50
The Chip Select Base Address register defines the base starting address for the chip
select.
Note:
9 2
Access Mnemonic
R/W AMUX2
N/A Reserved
The V bit is set to 1 on hardware reset for chip select 0 only.
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Reset Description
0 Internal/External/RAS/CAS mux
0 Normal operation
1 Drive the DRAM MUX control out PORTA2,
regardless of the AMUX and DMUXS settings
Used to drive the DRAM RAS/CAS address
multiplexing control signal out the PORTA2 pin,
regardless of the AMUX setting.
When set to 1, the memory controller drives the
DRAM RAS/CAS address multiplexing control
signal out the PORTA2 pin, for an external address
multiplexer to use for DRAM RAS/CAS address
multiplexing control.
N/A N/A