Digi NS7520B-1-C36 Hardware Reference Manual page 83

TIMEOUT = [4096 * (TC + 1)] / F
TIMEOUT = (TC + 1) / F
31 30 29 28
TE TIE TIRO TPRE TCLK
15 14 13 12
Register bit definition
Bits Access Mnemonic
D31 R/W TE
D30 R/W TIE
D29 R/W TIRO
D28 R/W TPRE
Table 27: Timer Control registers bit definition
XTALE
SYSCLK
27 26 25 24 23
11 10 9 8 7
ITC
Reset Description
0 Timer enable
1 Allows the timer to operate.
0 Resets and disables the timer.
The other fields in this register should be configured before
or during the same memory cycle in which TE is set to 1.
0 Timer interrupt enable
When set to 1, allows the timer to interrupt the CPU. A
timer interrupt is generated when the hardware sets the TIP
bit in the Timer Status register (see "Timer Status registers"
on page 73).
0 Timer interrupt mode
0 Normal interrupt
1 Fast interrupt
Controls the type of interrupt the timer asserts to the CPU.
0 Timer prescaler
0 Disable 9-bit prescaler
1 Enable 9-bit prescaler
Determines whether the 9-bit prescaler will be used in
calculating the TIMEOUT parameter. The prescaler allows
for longer TIMEOUT values.
TPRE affects TIMEOUT only when F
time source.
w w w . d i g i e m b e d d e d . c o m
G E N M o d u l e
TCLK = 0; TPRE = 1
TCLK = 1; TPRE = x
22 21 20 19 18
ITC
6 5 4 3 2
XTALE
17 16
1 0
is used as a
7 1