T i m i n g D i a g r a m s
JTAG timing
Operating conditions:
Temperature:
Voltage:
Output load:
Input drive:
jtag arm ice timing parameters
Num
54
55
56
57
58
60
61
jtag arm ice timing diagram
TCK
TDO
TDI
TRST_
TMS
2 9 2
-15.00 (min)
110.00 (max)
1.60 (min)
1.40 (max)
25.0pf
CMOS buffer
Description
TCK to TDO valid
TCK to TDO HighZ
TDI setup to TCK rising
TDI hold from TCK rising
TRST* width
TMS setup to TCK rising
TMS hold from TCK rising
54
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Min
Max
21
21
1
3
1
1
3
55
57
56
58
58
61
60
Units
ns
ns
ns
ns
T
TCK
ns
ns
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