Digi NS7520B-1-C36 Hardware Reference Manual page 252

S e r i a l C h a n n e l r e g i s t e r s
Bits
D05
D04
D03
D02
Table 89: Serial Channel Status Register A bit definition
2 4 0
Access Mnemonic
R/C DSRI
R/C CTSI
R TRDY
R THALF
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Reset Description
0 Change in DSR interrupt pending
Indicates a state change in the EIA data set ready
signal. Once set, the DSRI bit remains set until
acknowledged. DSRI is acknowledged by writing a 1
to this same bit position in this register.
The DSRI state condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
0 Change in CTS interrupt pending
Indicates a state change in the EIA clear to send
signal. Once set, the CTSI bit remains set until
acknowledged. CTSI is acknowledged by writing a 1
to this same bit position in this register.
The CTSI state condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
0 Transmit register empty interrupt pending
Indicates data can be written to the FIFO Data
register. TRDY typically is used only in interrupt-
driven applications; it is not used for DMA operation.
The TRDY status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
TRDY is never active while the TBC bit is active.
TBC must be acknowledged to activate the TRDY bit.
When the transmitter is configured to operate in DMA
mode, the interlock between TBC and TRDY is
handled automatically in hardware.
0 Transmit FIFO half-empty interrupt pending
Indicates that the transmit data FIFO contains room
for at least 16 bytes. The THALF field typically is
used only in interrupt-driven applications; it is not
used for DMA operation.
The THALF status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel COntrol Register A.