Memory Timing Fields - Sdram; Bsize Configuration - Digi NS7520B-1-C36 Hardware Reference Manual

S D R A M
Command
Load mode
Table 45: SDRAM command definitions
Memory timing fields — SDRAM
The WAIT configuration in the Chip Select Option register provides the SDRAM T
and T parameters. When WAIT is configured with a value of 0, the active and
RP
precharge commands can be followed immediately by another command on the next
active edge of BCLK. When WAIT is configured with a value larger than 0, wait states
are inserted after the active and precharge commands before another command can
be issued.
The BCYC configuration in the Chip Select Option register provides the SDRAM CAS
latency parameter. The BCYC field must be set to a value of
can support SDRAMs that have a CAS latency specification between 1 and 4 BCLK
clocks, as shown:
CAS latency
1
2
3
4

BSIZE configuration

The BSIZE configuration in the Chip Select Option register provides the SDRAM burst
length parameter. The BSIZE field is set as shown:
BSIZE
00
01
10
1 1 8
CSx_ A13:0 CAS3_ RAS#
0 Op-code 0
BCYC configuration
Do not use
01
10
11
Burst length
2 words (not supported)
4 words (not supported)
8 words (not supported)
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
CAS2_ CAS# CAS1_ WE#
0 0
CAS latency - 1
CAS0_ A10/AP
0
RCD
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