Digi NS7520B-1-C36 Hardware Reference Manual page 281

SRAM burst read
CS* controlled, four word (4-2-2-2), burst read (wait = 2, BCYC = 01)
T1
BCLK
TA* (Note-4)
TEA*/LAST (Note-4)
6
A[27:0]
36
BE[3:0]* (Note-2)
CS[4:0]*
read D[31:0]s
Sync OE*
CS0OE*
12
RW*
Notes:
If the next transfer is DMA, null periods between memory transfers can occur.
1
Thirteen clock pulses are required for DMA context switching.
Port size determines which byte enable signals are active:
2
8-bit port = BE3*
–
16-bit port = BE[3:0]
–
32-bit port = BE[3:0]
–
The TW cycles are present when the WAIT field is set to 2 or more.
3
The TA* and TEA*/LAST signals are for reference only.
4
TW TW T2 TW
30 30
27
11
10
28
18
w w w . d i g i e m b e d d e d . c o m
E l e c t r i c a l C h a r a c t e r i s t i c s
T2 TW T2 TW T2
31
Note-1 T1
31
36
27
28
18
2 6 9