Digi NS9750 Manuals

Manuals and User Guides for Digi NS9750. We have 2 Digi NS9750 manuals available for free PDF download: Hardware Reference Manual, Manual

Digi NS9750 Hardware Reference Manual (898 pages)

single chip 0.13μm CMOS network-attached processor

Brand: Digi | Category: Network Hardware | Size: 2.72 MB

Table of Contents

5
- About this Guide
  21
- Conventions Used in this Guide
  23
- Related Documentation
  23
- Customer Support
  24
- Chapter 1 : about NS9750
  
  26
  - NS9750 Features
    26
  - System-Level Interfaces
    32
  - System Boot
    34
  - Reset
    34
    
    RESET_DONE as an Input
    35
    
    RESET_DONE as an Output
    35
  - System Clock
    37
  - USB Clock
    39
- Chapter 2 : NS9750 Pinout
  
  42
  - Pinout and Signal Descriptions
    42
    
    System Memory Interface
    42
    
    System Memory Interface Signals
    46
    
    Ethernet Interface
    49
    
    Clock Generation/System Pins
    50
    
    Bist_En_N, Pll_Test_N, and Scan_En_N
    52
    
    PCI Interface
    52
    
    Gpio Mux
    58
    
    LCD Module Signals
    66
    
    USB Interface
    67
    
    JTAG Interface for ARM Core/Boundary Scan
    67
    
    Reserved
    69
    
    Power Ground
    70
- Chapter 3 : Working with the CPU
  
  72
  - About the Processor
    72
  - Instruction Sets
    73
    
    ARM Instruction Set
    74
    
    Thumb Instruction Set
    74
    
    Java Instruction Set
    74
  - System Control Processor (CP15) Registers
    75
    
    ARM926EJ-S System Addresses
    75
    
    Accessing CP15 Registers
    76
    
    Terms and Abbreviations
    76
    
    Register Summary
    77
    
    R0: ID Code and Cache Type Status Registers
    79
    
    R1: Control Register
    82
    
    R2: Translation Table Base Register
    85
    
    R3: Domain Access Control Register
    85
    
    R4 Register
    86
    
    R5: Fault Status Registers
    86
    
    R6: Fault Address Register
    88
    
    R7: Cache Operations Register
    88
    
    R8:TLB Operations Register
    92
    
    R9: Cache Lockdown Register
    93
    
    R10: TLB Lockdown Register
    97
    
    R11 and R12 Registers
    98
    
    R13: Process ID Register
    99
    
    R14 Register
    101
    
    R15: Test and Debug Register
    101
  - Jazelle (Java)
    101
  - Dsp
    102
  - Memory Management Unit (MMU)
    102
    
    MMU Features
    102
    
    Address Translation
    105
    
    MMU Faults and CPU Aborts
    119
    
    Domain Access Control
    122
    
    Fault Checking Sequence
    123
    
    External Aborts
    126
    
    Enabling the MMU
    127
    
    Disabling the MMU
    128
    
    TLB Structure
    128
  - Caches and Write Buffer
    129
    
    Cache Features
    129
    
    Write Buffer
    130
    
    Enabling the Caches
    131
    
    Cache MVA and Set/Way Formats
    133
  - Noncachable Instruction Fetches
    135
    
    Self-Modifying Code
    136
    
    AHB Behavior
    136
  - Instruction Memory Barrier
    137
    
    IMB Operation
    137
    
    Sample IMB Sequences
    138
- Chapter 5 : M E M O R y C O N T R O L L E R
  
  138
  - Memory Controller
    139
  - System Overview
    141
  - Low-Power Operation
    142
  - Memory Map
    142
  - Static Memory Controller
    145
    
    More Information
    145
    
    Write Protection
    146
    
    Extended Wait Transfers
    146
    
    Memory Mapped Peripherals
    147
    
    Static Memory Initialization
    147
    
    Byte Lane Control
    173
    
    Address Connectivity
    174
    
    Byte Lane Control and Databus Steering
    178
  - Dynamic Memory Controller
    186
    
    Write Protection
    186
    
    Access Sequencing and Memory Width
    186
    
    Address Mapping
    187
  - Registers
    226
    
    Register Map
    226
    
    Reset Values
    228
    
    Control Register
    229
    
    Status Register
    231
    
    Configuration Register
    231
    
    Dynamic Memory Control Register
    232
    
    Dynamic Memory Refresh Timer Register
    234
    
    Dynamic Memory Read Configuration Register
    236
    
    Dynamic Memory Precharge Command Period Register
    237
    
    Dynamic Memory Active to Precharge Command Period Register
    238
    
    Dynamic Memory Self-Refresh Exit Time Register
    239
    
    Dynamic Memory Last Data out to Active Time Register
    240
    
    Dynamic Memory Data-In to Active Command Time Register
    241
    
    Dynamic Memory Write Recovery Time Register
    242
    
    Dynamic Memory Active to Active Command Period Register
    243
    
    Dynamic Memory Auto Refresh Period Register
    244
    
    Dynamic Memory Exit Self-Refresh Register
    245
    
    Dynamic Memory Active Bank a to Active Bank B Time Register
    246
    
    Dynamic Memory Load Mode Register to Active Command Time Register
    247
    
    Static Memory Extended Wait Register
    248
    
    Dynamic Memory Configuration 0-3 Registers
    249
    
    Dynamic Memory RAS and CAS Delay 0-3 Registers
    253
    
    Static Memory Configuration 0-3 Registers
    254
    
    Static Memory Write Enable Delay 0-3 Registers
    258
    
    Static Memory Output Enable Delay 0-3 Registers
    259
    
    Static Memory Read Delay 0-3 Registers
    260
    
    Static Memory Page Mode Read Delay 0-3 Registers
    261
    
    Static Memory Write Delay 0-3 Registers
    262
    
    Static Memory Turn Round Delay 0-3 Registers
    263
    
    System Control Module
    277
- Chapter 4 : System Control Module
  
  278
  - Bus Interconnection
    278
  - System Bus Arbiter
    278
    
    Arbiter Configuration Examples
    279
  - System Control Module Features
    278
  - Address Decoding
    281
    
    Address Decoding
    285
  - Programmable Timers
    287
    
    Software Watchdog Timer
    287
    
    General Purpose Timers/Counters
    287
  - Interrupt Controller
    288
  - Registers
    288
    
    Interrupt Controller
    291
    
    Vectored Interrupt Controller (VIC) Flow
    294
  - System Attributes
    295
    
    PLL Configuration
    295
    
    Bootstrap Initialization
    295
    
    System Configuration Registers
    296
  - System Configuration Registers
    300
    
    AHB Arbiter Gen Configuration Register
    306
    
    BRC0, BRC1, BRC2, and BRC3 Registers
    307
    
    Timer 0–15 Reload Count Registers
    308
    
    Timer 0–15 Read Register
    309
    
    Int (Interrupt) Config (Configuration) Registers (0–31)
    310
    
    Register Bit Assignment
    311
    
    ISRADDR Register
    312
    
    Interrupt Status Active
    313
    
    Timer 0–15 Control Registers
    325
    
    External Interrupt 0–3 Control Register
    337
    
    Ethernet Communication
    339
    
    Overview
    340
    
    Ethernet MAC
    341
    
    Station Address Logic (SAL)
    345
    
    Statistics Module
    345
    
    Ethernet Front-End Module
    347
    
    Receive Packet Processor
    348
    
    Transmit Packet Processor
    351
    
    Ethernet Slave Interface
    354
    
    Interrupts
    355
    
    Resets
    356
    
    External CAM Filtering
    358
  - Ethernet Control and Status Registers
    361
    
    Ethernet General Control Register #1
    363
    
    Ethernet General Control Register #2
    366
    
    Ethernet General Status Register
    368
    
    Ethernet Transmit Status Register
    368
    
    Ethernet Receive Status Register
    371
    
    MAC Configuration Register #1
    372
    
    MAC Configuration Register #2
    375
    
    Pad Operation Table for Transmit Frames
    377
    
    Back-To-Back Inter-Packet-Gap Register
    378
    
    Non Back-To-Back Inter-Packet-Gap Register
    379
    
    Collision Window/Retry Register
    379
    
    Maximum Frame Register
    381
    
    PHY Support Register
    382
    
    MII Management Configuration Register
    383
    
    MII Management Command Register
    384
    
    MII Management Address Register
    385
    
    MII Management Write Data Register
    386
    
    MII Management Read Data Register
    387
    
    MII Management Indicators Register
    387
    
    Station Address Registers
    388
    
    Station Address Filter Register
    390
    
    Register Hash Tables
    390
    
    Statistics Registers
    392
    
    RX_A Buffer Descriptor Pointer Register
    407
    
    RX_B Buffer Descriptor Pointer Register
    407
    
    RX_C Buffer Descriptor Pointer Register
    408
    
    RX_D Buffer Descriptor Pointer Register
    408
    
    Ethernet Interrupt Status Register
    409
    
    Ethernet Interrupt Enable Register
    411
    
    TX Buffer Descriptor Pointer Register
    413
    
    Transmit Recover Buffer Descriptor Pointer Register
    413
    
    TX Error Buffer Descriptor Pointer Register
    414
    
    RX_A Buffer Descriptor Pointer Offset Register
    415
    
    RX_B Buffer Descriptor Pointer Offset Register
    416
    
    RX_C Buffer Descriptor Pointer Offset Register
    417
    
    RX_D Buffer Descriptor Pointer Offset Register
    417
    
    Transmit Buffer Descriptor Pointer Offset Register
    418
    
    RX Free Buffer Register
    419
    
    TX Buffer Descriptor RAM
    420
  - Sample Hash Table Code
    421
- Chapter 7 : PCI-To-AHB Bridge
  
  428
  - About the PCI-To-AHB Bridge
    428
    
    PCI-To-AHB Bridge Functionality
    429
    
    Cross-Bridge Transaction Error Handling
    431
    
    AHB Address Decoding and Translation
    432
    
    PCI Address Decoding and Mapping
    432
    
    Interrupts
    433
    
    Transaction Ordering
    434
    
    Endian Configuration
    435
    
    Configuration Registers
    435
    
    Bridge Configuration Registers
    437
  - PCI Bus Arbiter
    442
    
    PCI Arbiter Functional Description
    443
    
    Slave Interface
    444
    
    PCI Arbiter Configuration Registers
    444
  - PCI System Configurations
    480
    
    Device Selection for Configuration
    482
    
    PCI Interrupts
    482
    
    PCI Central Resource Functions
    482
  - Cardbus Support
    485
    
    Configuring NS9750 for Cardbus Support
    487
    
    Cardbus Adapter Requirements
    488
    
    Cardbus Interrupts
    489
- Chapter 8 : Bbus Bridge
  
  492
  - Bbus Bridge Functions
    492
  - Bridge Control Logic
    493
    
    DMA Accesses
    495
  - Bbus Control Logic
    496
    
    Bbus Bridge Masters and Slaves
    496
    
    Cycles and Bbus Arbitration
    497
    
    Bbus Peripheral Address Map (Decoding)
    497
  - Two-Channel AHB DMA Controller (AHB Bus)
    498
    
    DMA Buffer Descriptor
    498
    
    Descriptor List Processing
    500
    
    Peripheral DMA Read Access
    501
    
    Peripheral DMA Write Access
    502
    
    Peripheral REQ Signaling
    503
    
    Design Limitations
    504
    
    Calculating AHB DMA Response Latency
    504
    
    Static RAM Chip Select Configuration
    506
  - Bandwidth Requirements
    507
  - Interrupt Aggregation
    507
  - SPI-EEPROM Boot Logic
    508
    
    Serial Channel B Configuration
    509
    
    Memory Controller Configuration
    510
    
    SDRAM Boot Algorithm
    512
  - Bbus Bridge Control and Status Registers
    514
    
    Buffer Descriptor Pointer Register
    515
    
    DMA Channel 1/2 Control Register
    515
    
    DMA Status and Interrupt Enable Register
    518
    
    DMA Peripheral Chip Select Register
    520
    
    Bbus Bridge Interrupt Status Register
    522
    
    Bbus Bridge Interrupt Enable Register
    523
- Chapter 9 : Bbus DMA Controller
  
  526
  - About the Bbus DMA Controllers
    526
  - DMA Context Memory
    527
  - DMA Buffer Descriptor
    528
  - DMA Channel Assignments
    533
  - DMA Control and Status Registers
    534
    
    DMA Buffer Descriptor Pointer
    536
    
    DMA Control Register
    538
    
    DMA Status/Interrupt Enable Register
    540
- Chapter 10 : Bbus Utility
  
  546
  - Bbus Utility Control and Status Registers
    546
    
    Master Reset Register
    547
    
    GPIO Configuration Registers
    548
    
    GPIO Control Registers
    553
    
    GPIO Status Registers
    556
    
    Bbus Monitor Register
    559
    
    Bbus DMA Interrupt Status Register
    560
    
    Bbus DMA Interrupt Enable Register
    561
    
    USB Configuration Register
    562
    
    Endian Configuration Register
    563
    
    ARM Wake-Up Register
    565
- Chapter 16 : USB Controller Module
  
  568
  - Overview
    568
- Chapter 11 : I2C Master/Slave Interface
  
  570
  - Locked Interrupt Driven Mode
    570
  - Master Module and Slave Module Commands
    570
  - Bus Arbitration
    571
  - Command Transmit Data Register
    572
  - Status Receive Data Register
    573
  - Master Address Register
    574
  - Slave Address Register
    575
  - Configuration Register
    576
  - Interrupt Codes
    577
  - Software Driver
    579
    
    Master Module (Normal Mode, 16-Bit)
    580
  - Flow Charts
    580
    
    Slave Module (Normal Mode, 16-Bit)
    581
    
    Lcd Controller
    583
    
    Programmable Parameters
    584
- Chapter 12 : LCD Controller
  
  584
  - LCD Features
    584
    
    LCD Panel Resolution
    585
    
    LCD Panel Support
    585
    
    Number of Colors
    586
    
    LCD Power up and Power down Sequence Support
    587
  - LCD Controller Functional Overview
    588
    
    Clocks
    589
    
    Signals and Interrupts
    590
    
    AHB Master and Slave Interfaces
    592
    
    Dual DMA Fifos and Associated Control Logic
    592
  - AHB Interface
    592
    
    Pixel Serializer
    593
    
    RAM Palette
    597
    
    Grayscaler
    598
    
    Upper and Lower Panel Formatters
    598
    
    Panel Clock Generator
    598
    
    Timing Controller
    598
    
    Generating Interrupts
    599
    
    External Pad Interface Signals
    599
    
    LCD Panel Signal Multiplexing Details
    599
    
    Registers
    603
    
    Lcdtiming0
    604
    
    Lcdtiming1
    606
    
    Lcdtiming2 Register
    607
    
    Lcdtiming3
    611
    
    LCDUPBASE and LCDLPBASE
    611
    
    Lcdintrenable
    613
    
    Lcdcontrol Register
    614
    
    Lcdstatus Register
    617
    
    Lcdinterrupt Register
    618
    
    LCDUPCURR and LCDLPCURR
    618
    
    Lcdpalette Register
    619
    
    Interrupts
    622
    
    MBERRORINTR — Master Bus Error Interrupt
    622
    
    VCOMPINTR — Vertical Compare Interrupt
    622
    
    LBUINTR — Next Base Address Update Interrupt
    623
    
    Features
    626
    
    Bit-Rate Generator
    627
- Chapter 13 : Serial Control Module: UART
  
  628
  - UART Mode
    628
    
    FIFO Management
    629
    
    Transmit FIFO Interface
    629
    
    Receive FIFO Interface
    630
  - Serial Port Control and Status Registers
    632
    
    Serial Channel B/A/C/D Control Register a
    635
    
    Serial Channel B/A/C/D Control Register B
    638
    
    Serial Channel B/A/C/D Status Register a
    641
    
    Serial Channel B/A/C/D Bit-Rate Register
    648
    
    Serial Channel B/A/C/D FIFO Data Register
    653
    
    Serial Channel B/A/C/D Receive Buffer GAP Timer
    654
    
    Serial Channel B/A/C/D Receive Character GAP Timer
    656
    
    Serial Channel B/A/C/D Receive Match Register
    658
    
    Serial Channel B/A/C/D Receive Match MASK Register
    659
    
    Serial Channel B/A/C/D Flow Control Register
    660
    
    Serial Channel B/A/C/D Flow Control Force Register
    662
    
    Features
    668
    
    Bit-Rate Generator
    669
- Chapter 14 : Serial Control Module: SPI
  
  670
  - Serial Port Performance
    632
  - SPI Mode
    670
    
    SPI Modes
    670
    
    Transmit FIFO Interface
    671
  - FIFO Management
    671
    
    Receive FIFO Interface
    672
    
    Serial Port Control and Status Registers
    674
  - Serial Port Performance
    674
    
    Serial Channel B/A/C/D Control Register a
    676
    
    Serial Channel B/A/C/D Control Register B
    679
    
    Serial Channel B/A/C/D Status Register a
    681
    
    Serial Channel B/A/C/D Bit-Rate Register
    684
    
    Serial Channel B/A/C/D FIFO Data Register
    689
- Chapter 15 : IEEE 1284 Peripheral Controller
  
  694
  - Requirements
    694
    
    Overview
    694
    
    Compatibility Mode
    695
    
    Nibble Mode
    696
    
    Byte Mode
    696
    
    ECP Mode
    697
    
    Data and Command Fifos
    699
    
    IEEE 1284 Negotiation
    700
    
    Bbus Slave and DMA Interface Register Map
    701
    
    IEEE 1284 General Configuration Register
    703
    
    Interrupt Status and Control Register
    705
    
    FIFO Status Register
    708
    
    Forward Command FIFO Read Register
    710
    
    Forward Data FIFO Read Register
    711
    
    Reverse FIFO Write Register/Reverse FIFO Write Register — Last
    711
    
    Forward Command DMA Control Register
    713
    
    Forward Data DMA Control Register
    714
    
    Printer Data Pins Register
    715
    
    Port Status Register, Host
    716
    
    Port Control Register
    717
    
    Port Status Register, Peripheral
    718
    
    Feature Control Register a
    718
    
    Feature Control Register B
    719
    
    Interrupt Enable Register
    719
    
    Master Enable Register
    721
    
    Extensibility Byte Requested by Host
    722
    
    Extended Control Register
    722
    
    Interrupt Status Register
    723
    
    Pin Interrupt Mask Register
    724
    
    Pin Interrupt Control Register
    725
    
    Granularity Count Register
    726
    
    Forward Address Register
    727
    
    Core Phase (IEEE1284) Register
    728
  - USB Module Architecture
    732
    
    Overview
    732
  - USB Device Block
    734
    
    Control and Status
    734
    
    Packet and Data Flow
    735
    
    Logical and Physical Endpoints
    736
    
    Slew Rates
    736
  - Host Block
    736
    
    Control and Status
    736
    
    Packet Data Flow
    737
  - Transmission Error Handling
    738
    
    Handling USB-IN Packet Errors
    739
    
    Handling USB-OUT Packet Errors
    739
  - USB Device Endpoint
    738
  - USB Block Registers
    740
  - USB Global Registers
    740
    
    Global Control and Status Register
    741
    
    Device Control and Status Register
    742
    
    Global Interrupt Enable Register
    744
    
    Global Interrupt Status Register
    745
    
    Device IP Programming Control/Status Register
    748
  - USB Host Block Registers
    749
    
    Reserved Bits
    749
    
    USB Host Block Register Address Map
    749
    
    Hcrevision Register
    750
    
    Hccontrol Register
    751
    
    Hccommandstatus Register
    754
    
    Hcinterruptstatus Register
    757
    
    Hcinterruptenable Register
    759
    
    Hcinterruptdisable Register
    761
    
    Hchcca Register
    763
    
    Hcperiodcurrented Register
    764
    
    Hccontrolheaded Register
    765
    
    Hccontrolcurrented Register
    766
    
    Hcbulkheaded Register
    767
    
    Hcbulkcurrented Register
    768
    
    Hcdonehead Register
    770
    
    Hcfminterval Register
    771
    
    Hcfmremaining Register
    772
    
    Hcfmnumber Register
    773
    
    Hcperiodicstart Register
    774
    
    Hclsthreshold Register
    775
    
    Root Hub Partition Registers
    776
    
    Hcrhdescriptora Register
    777
    
    Hcrhdescriptorb Register
    779
    
    Hcrhstatus Register
    780
    
    Hcrhportstatus[1] Register
    783
  - USB Device Block Registers
    789
    
    Device Descriptor/Setup Command Register
    789
    
    Endpoint Descriptor #0–#11 Registers
    790
  - USB Device Endpoint FIFO Control and Data Registers
    791
    
    FIFO Interrupt Status Registers
    793
    
    Fifo Interrupt Status 0 Register
    795
    
    Fifo Interrupt Status 1 Register
    795
    
    Fifo Interrupt Status 2 Register
    797
    
    Fifo Interrupt Status 3 Register
    799
    
    FIFO Interrupt Enable Registers
    800
    
    Fifo Interrupt Enable 0 Register
    800
    
    Fifo Interrupt Enable 1 Register
    801
    
    FIFO Packet Control Registers
    804
    
    FIFO Status and Control Registers
    805
- Chapter 17 : Timing
  
  812
  - Electrical Characteristics
    812
    
    Absolute Maximum Ratings
    812
    
    Recommended Operating Conditions
    812
    
    Maximum Power Dissipation
    813
    
    Typical Power Dissipation
    813
  - DC Electrical Characteristics
    814
    
    Inputs
    814
    
    Outputs
    815
  - Reset and Edge Sensitive Input Timing Requirements
    816
  - Power Sequencing
    818
  - Memory Timing
    819
    
    SDRAM Burst Read (16-Bit)
    820
    
    SDRAM Burst Read (16-Bit), CAS Latency = 3
    821
    
    SDRAM Burst Write (16-Bit)
    822
    
    SDRAM Burst Read (32-Bit)
    823
    
    SDRAM Burst Read (32-Bit), CAS Latency = 3
    824
    
    SDRAM Burst Write (32-Bit)
    825
    
    SDRAM Load Mode
    826
    
    SDRAM Refresh Mode
    827
    
    Clock Enable Timing
    827
    
    Static RAM Read Cycles with 0 Wait States
    829
    
    Static RAM Asynchronous Page Mode Read, WTPG = 1
    830
    
    Static RAM Read Cycle with Configurable Wait States
    831
    
    Static RAM Sequential Write Cycles
    832
    
    Static RAM Write Cycle
    833
    
    Static Write Cycle with Configurable Wait States
    834
    
    Slow Peripheral Acknowledge Timing
    835
    
    Slow Peripheral Acknowledge Read
    836
    
    Slow Peripheral Acknowledge Write
    836
    
    Ethernet Timing
    837
    
    Ethernet MII Timing
    838
    
    Ethernet RMII Timing
    839
  - PCI Timing
    840
    
    Internal PCI Arbiter Timing
    842
    
    PCI Burst Write from NS9750 Timing
    842
    
    PCI Burst Read from NS9750 Timing
    843
    
    PCI Burst Write to NS9750 Timing
    843
    
    PCI Burst Read to NS9750 Timing
    844
    
    PCI Clock Timing
    844
  - LCD Timing
    846
    
    Horizontal Timing for STN Displays
    848
    
    Vertical Timing for STN Displays
    849
    
    Horizontal Timing for TFT Displays
    849
    
    Vertical Timing for TFT Displays
    849
    
    HSYNC Vs VSYNC Timing for STN Displays
    850
    
    HSYNC Vs VSYNC Timing for TFT Displays
    850
    
    LCD Output Timing
    850
  - SPI Timing
    851
    
    SPI Master Mode 0 and 1: 2-Byte Transfer
    853
    
    SPI Master Mode 2 and 3: 2-Byte Transfer
    853
    
    SPI Slave Mode 0 and 1: 2-Byte Transfer
    854
    
    SPI Slave Mode 2 and 3: 2-Byte Transfer
    854
  - IEEE 1284 Timing
    855
    
    IEEE 1284 Timing Example
    855
  - USB Timing
    856
    
    USB Differential Data Timing
    857
    
    USB Full Speed Load Timing
    857
    
    USB Low Speed Load
    858
  - Reset and Hardware Strapping Timing
    859
  - JTAG Timing
    860
  - Clock Timing
    861
    
    USB Crystal/External Oscillator Timing
    861
    
    LCD Input Clock Timing
    862
    
    System PLL Bypass Mode Timing
    863
- Chapter 18 : Packaging
  
  869
  - Product Specifications
    869
Table of Contents

878
- I2C Timing
  880
  - Write Protection
    884
  - Extended Wait Transfers
    891
- Features
  892
  - Static Memory Controller
    895
  - Write Protection
    895
  - Control Register
    895
  - Status Register
    895
  - Dynamic Memory Controller
    895

Digi NS9750 Manual (24 pages)

Jumpers and Components

Brand: Digi | Category: Motherboard | Size: 1.04 MB

Table of Contents
5
Overview
12
- NS9750 Development Board Features
  12
GPIO-Related Configurations
13
Non GPIO-Related Configurations
15
- Serial Port a 422/485 Mode
  15
- PCI Cardbus
  15
- Mini-PCI
  15
- Rmii
  16
- PCI or Cardbus
  16
Default Configuration Switch Settings
17
Configuration Register Switch Settings
19

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Network Router Control Unit Modem Gateway Server

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Digi NS9750 Manuals

Digi NS9750 Hardware Reference Manual (898 pages)

Table of Contents

Table of Contents

Chapter 1 : about NS9750

Chapter 2 : NS9750 Pinout

Chapter 3 : Working with the CPU

Chapter 5 : M E M O R y C O N T R O L L E R

Chapter 4 : System Control Module

Chapter 7 : PCI-To-AHB Bridge

Chapter 8 : Bbus Bridge

Chapter 9 : Bbus DMA Controller

Chapter 10 : Bbus Utility

Chapter 16 : USB Controller Module

Chapter 11 : I2C Master/Slave Interface

Chapter 12 : LCD Controller

Chapter 13 : Serial Control Module: UART

Chapter 14 : Serial Control Module: SPI

Chapter 15 : IEEE 1284 Peripheral Controller

Chapter 17 : Timing

Chapter 18 : Packaging

Table of Contents

Digi NS9750 Manual (24 pages)

Table of Contents

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