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Digi NS7520B-1-C36 Hardware Reference Manual

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Part number/version: 90000353_G
Release date: September 2007
www.digiembedded.com
NS7520 Hardware Reference

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Summary of Contents for Digi NS7520B-1-C36

  • Page 1 Part number/version: 90000353_G Release date: September 2007 www.digiembedded.com NS7520 Hardware Reference...
  • Page 2 Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of, fitness or merchantability for a particular purpose. Digi may make improvements and/or changes in this manual or in the product(s) and/or the program(s) described in this manual at any time.
  • Page 3 Using This Guide Using This Guide This guide provides information about the NS7520 32-bit networked microprocessor. The NS7520 is part of the NET+ARM line of SoC (System-on- Chip) products, and supports high-bandwidth applications for intelligent networked devices. The NET+ARM family is part of the NET+Works integrated product family, which includes the NET+OS network software suite.
  • Page 4 For additional documentation, see the Documentation folder in the NET+OS Start menu. Documentation updates Digi occasionally provides documentation updates on the Web site (www.digiembedded.com/support). Be aware that if you see differences between the documentation you received in your package and the documentation on the Web site, the Web site content is the latest version.

  • Page 5: Table Of Contents

    Contents C h a p t e r 1 : A b o u t t h e N S 7 5 2 0 ..................1 NS7520 Features ................. 2 Key features and operating modes of the major NS7520 modules ..2 NS7520 module block diagram............
  • Page 6 Exception vector table............33 Detail of ARM exceptions ............34 Entering and exiting an exception (software action) ...... 37 Hardware Interrupts..............39 FIRQ and IRQ lines ............... 39 Interrupt controller.............. 39 Interrupt sources..............40 C h a p t e r 4 : B B u s M o d u l e ....................43 BBus masters and slaves ...............
  • Page 7 System Control register ............63 System Status register ............68 Software Service register............69 Timer Control registers ............70 Timer Status registers............73 PORTA Configuration register..........73 PORTC Configuration register..........77 Interrupts ................80 Interrupt controller registers ..........81 C h a p t e r 7 : M e m o r y C o n t r o l l e r M o d u l e ............
  • Page 8 SDRAM read cycles..............120 SDRAM write cycles .............122 Peripheral page burst size ............124 C h a p t e r 8 : D M A M o d u l e ....................127 DMA module ................128 Fly-by operation transfers.............128 Memory-to-memory operation ..........129 DMA buffer descriptor ..............130 DMA channel assignments ............132 DMA channel registers ..............133...
  • Page 9 Ethernet General Status register (EGSR) bit definitions ....164 Ethernet FIFO Data register ...........167 Ethernet Transmit Status register..........168 Ethernet Receive Status register ..........173 MAC Configuration Register 1 ..........176 MAC Configuration Register 2 ..........178 Back-to-Back Inter-Packet-Gap register........182 Non-Back-to-Back Inter-Packet-Gap register .......183 Collision Window/Collision Retry register ........184 Maximum Frame register ............185 PHY Support register ............186 Test register ..............187...
  • Page 10 Serial Channel 1, 2 Bit-Rate registers ........241 Serial Channel 1, 2 FIFO registers ..........250 Serial Channel 1, 2 Receive Buffer Gap Timer ......250 Serial Channel 1, 2 Receive Character Gap Timer......252 Serial Channel 1,2 Receive Match register........254 Serial Channel 1, 2 Receive Match MASK register......254 C h a p t e r 1 1 : E l e c t r i c a l C h a r a c t e r i s t i c s ............257 DC characteristics ..............258...
  • Page 11 Error in “No Connect” pin terminations........308 Serial port error in 7-bit mode ..........309 SDRAM 256 MB mask failure ...........309 Erroneous timeouts when loading timer ........309 Station Address Logic: Multicast and broadcast packet filtering ..310 Station Address Logic: Unicast packets ........310 Corrupt Ethernet receive packets..........311 Transmit buffer closed bit is not functional ........312 Transmit FIFO timing issue ............312...

  • Page 13: Chapter 1 : A B O U T T H E N S 7 5 2 0

    A b o u t t h e N S 7 5 2 0 About the NS7520 his chapter provides an overview of the NS7520. The NS7520 is a high- performance, highly integrated, 32-bit system-on-a-chip ASIC designed for use in intelligent networked devices and Internet appliances.

  • Page 14: Ns7520 Features

    N S 7 5 2 0 F e a t u r e s NS7520 Features The NS7520 can support most any networking scenario, and includes a 10/100 BaseT Ethernet MAC and two independent serial ports (each of which can run in UART or SPI mode).
  • Page 15 A b o u t t h e N S 7 5 2 0 General-purpose I/O pins – 16 programmable GPIO interface pins Four pins programmable with level-sensitive interrupt – Serial ports Two fully independent serial ports (UART, SPI) – Digital phase lock loop (DPLL) for receive clock extractions –...
  • Page 16 N S 7 5 2 0 F e a t u r e s Programmable timers – Two independent timers (2μs–20.7 hours) Watchdog timer (interrupt or reset on expiration) – Programmable bus monitor or timer – Operating frequency 36, 46, or 55 MHz internal clock operation from 18.432 MHz quartz crystal –...

  • Page 17: Ns7520 Module Block Diagram

    A b o u t t h e N S 7 5 2 0 NS7520 module block diagram Figure 1 is an overview of the NS7520, including all the modules. Debugger JTAG Debug NS7520 Reset Interface System FIRQ Clock ARM7TDMI Watchdog 2 timers timer...

  • Page 18: Operating Frequency

    O p e r a t i n g f r e q u e n c y Operating frequency The NS7520 is available in grades operating at three maximum operating frequencies: 36 MHz, 46 MHz, and 55 MHz. The operating frequency is set during bootstrap initialization, using pins A[8:0].
  • Page 19 P i n o u t a n d P a c k a g i n g Pinout and Packaging he NS7520 can be used in any embedded environment requiring networking services in an Ethernet LAN. The NS7520 contains an integrated ARM RISC processor, 10/100 Ethernet MAC, serial ports, memory controllers, and parallel I/O.

  • Page 20: Packaging

    P a c k a g i n g Packaging Table 1 provides the NS7520 packaging dimensions. Figure 2 shows the pinout and NS7520 dimensions. Figure 3 shows the NS7520 BGA layout. Symbol — — 0.35 0.40 0.45 — — 0.95 0.45 0.50...
  • Page 21 P i n o u t a n d P a c k a g i n g 177 PFBGA Figure 2: NS7520 pinout and dimensions w w w . d i g i e m b e d d e d . c o m...
  • Page 22 P a c k a g i n g GNDPY13 CAS3_ GNDPY1 VCCPY4 GNDPY8 VSSOSC2 CAS0_ VCCPY2 VCCPY1 OSCVCC2 CAS1_ VCCPY9 GNDPY2 VCCPY5 GNDPY5 VCCPY8 CAS2_ CS4_ CS3_ VCCPY3 GUIDE PIN CS0_ CS2_ CS1_ GNDPY9 BCLK GNDPY3 BUSY_ GNDPY10 NS7520, 177 PFBGA VDDC01 GNDPY4 TEA_...

  • Page 23: Pinout Detail Tables And Signal Descriptions

    P i n o u t a n d P a c k a g i n g Pinout detail tables and signal descriptions Each pinout table applies to a specific interface and contains the following information: Column Description Signal The pin name for each I/O signal.

  • Page 24: System Bus Interface

    P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s System bus interface Symbol Description BCLK...
  • Page 25 P i n o u t a n d P a c k a g i n g Symbol Description ADDR6 R2 U ADDR5 M4 U ADDR4 N4 U ADDR3 R1 U ADDR2 M3 U ADDR1 N2 U ADDR0 P1 U DATA31 Data bus DATA30...
  • Page 26 P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s Symbol Description DATA11 DATA10...
  • Page 27 P i n o u t a n d P a c k a g i n g Symbol Description NO CONNECT BUSY_ NO CONNECT Table 2: System bus interface pinout Signal descriptions Mnemonic Signal Description BCLK Bus clock Provides the bus clock. All system bus interface signals are referenced to the BCLK signal.

  • Page 28: Chip Select Controller

    P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s Mnemonic Signal Description TEA_...
  • Page 29 P i n o u t a n d P a c k a g i n g Symbol Description CAS1_ FP/EDO DRAM column strobe D15:D08/SDRAM WE_ CAS0_ FP/EDO DRAM column strobe D07:D00/SDRAM A10(AP) Write enable for NCC Ctrl’d cycles Output enable for NCC Ctrl’d cycles Table 4: Chip select controller pinout Signal descriptions...

  • Page 30: Ethernet Interface Mac

    P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s Mnemonic Signal Description Output enable...
  • Page 31 P i n o u t a n d P a c k a g i n g Symbol Description RXD2 GP input RX data 2 Read state in bit 15 RXD1 GP input RX data 1 Read state in bit 13 RXD0 RX data 0 Receive data...
  • Page 32 P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s Mnemonic Signal Description Transmit collision...

  • Page 33: No Connect" Pins

    P i n o u t a n d P a c k a g i n g “No connect” pins Description Add a 15K ohm pulldown to GND (15K ohm is the recommended value; 10– 20K ohms is acceptable) Add a 15K ohm pulldown to GND (15K ohm is the recommended value;...
  • Page 34 P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s GPIO Serial Other Serial channel...
  • Page 35 P i n o u t a n d P a c k a g i n g GPIO Serial Other Serial channel Other signal signal signal description description PORTC1 CTSB_ LIRQ1/ E12 U Channel 2 CTS_ Level sensitive DONE2_ IRQ/DMA channel 4/6 DONE_out...

  • Page 36: System Clock And Reset

    P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s System clock and reset Symbol Description XTALA1...

  • Page 37: System Mode (Test Support)

    P i n o u t a n d P a c k a g i n g This figure shows the timing and specification for RESET_ rise/fall times: tF max = 18ns tR max = 18ns Vin = 2.0V to 0.8V Vin = 0.8V to 2.0V System mode (test support) PLLTST_, BISTEN_, and SCANEN_ primary inputs control different test modes for both...

  • Page 38: Jtag Test (Arm Debugger)

    P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s JTAG test (ARM debugger) JTAG boundary scan allows a tester to check the soldering of all signal pins and tri- state all outputs.
  • Page 39 P i n o u t a n d P a c k a g i n g Mnemonic Signal Description TRST_ Test mode reset TRST_ operates the JTAG standard. Consult the JTAG specifications for use in boundary-scan testing. These signals meet the requirements of the Raven and Jeeni debuggers.

  • Page 40: Power Supply

    P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s Power supply Signal Description Oscillator VCC (3.3V)
  • Page 41 W o r k i n g w i t h t h e C P U Working with the CPU he CPU uses an ARM7TDMI core processor, which provides high performance while maintaining low power consumption and small size. This chapter describes the ARM Thumb concept and provides an overview of ARM exceptions and hardware interrupts.

  • Page 42: Arm Thumb Concept

    A R M T h u m b c o n c e p t ARM Thumb concept The ARM7TDMI processor uses a unique architectural strategy known as Thumb, which makes the processor ideally suited to high-volume applications with memory restrictions or applications for which code density is an issue.

  • Page 43: Working With Arm Exceptions

    W o r k i n g w i t h t h e C P U The ARM instruction set yields a 0.9 Dhrystone (2.1) rating MIPS/MHz of instruction executions; the Thumb instruction set yields 0.75 Dhrystones MIPS/MHz. The MHz rating reflects the rate at which instructions can be fetched from external flash memory, as shown in this table: System bus...

  • Page 44: Summary Of Arm Exceptions

    W o r k i n g w i t h A R M e x c e p t i o n s Summary of ARM exceptions The ARM processor can be interrupted by any of seven basic exceptions: Reset exception.

  • Page 45: Exception Vector Table

    W o r k i n g w i t h t h e C P U Not all exceptions can occur at the same time, however. Undefined instructions and SWIs are mutually exclusive, as they each correspond to particular (non-overlapping) decoding of the current instruction.

  • Page 46: Detail Of Arm Exceptions

    W o r k i n g w i t h A R M e x c e p t i o n s All internal ARM7TDMI internal peripherals are presented to the CPU using the IRQ or FIRQ interrupt inputs. The ARM can mask various ARM7TDMI peripheral interrupts at the global level, using the ARM7TDMI interrupt controller.
  • Page 47 W o r k i n g w i t h t h e C P U After emulating the failed instruction, the trap handler should execute the following instruction irrespective of the state (Thumb or ARM): MOVS PC, R14_und. This instruction restores the PC and CPSR, and returns to the instruction following the undefined instruction.
  • Page 48 W o r k i n g w i t h A R M e x c e p t i o n s The abort mechanism allows the implementation of a demand-paged virtual memory system. In this type of system, the processor is allowed to generate arbitrary addresses.

  • Page 49: Entering And Exiting An Exception (Software Action)

    W o r k i n g w i t h t h e C P U Entering and exiting an exception (software action) The ARM7TDMI performs specific steps when handling exceptions. Entering an exception When handling an exception, ARM7TDMI does this: Preserves the address of the next instruction in the appropriate Link register.
  • Page 50 W o r k i n g w i t h A R M e x c e p t i o n s An explicit switch back to Thumb state is never needed. Restoring the Note: CPSR from the SPSR automatically sets the T bit to the value it held immediately before the exception.

  • Page 51: Hardware Interrupts

    W o r k i n g w i t h t h e C P U Hardware Interrupts Two wires that go into the ARM7 CPU core can interrupt the processor: IRQ (normal interrupt) FIRQ (fast interrupt) Although the interrupts are basically the same, FIRQ can interrupt IRQ. FIRQ and IRQ lines The FIRQ line adds a simple, two-tier priority scheme to the interrupt system.

  • Page 52: Interrupt Sources

    H a r d w a r e I n t e r r u p t s Interrupt Status Register Enabled. Identifies the current state of all interrupt sources that are enabled. This register is defined by performing a logical AND of the Interrupt Status Register Raw and the Interrupt Enable register.
  • Page 53 W o r k i n g w i t h t h e C P U PORTC interrupts. The lower four pins of PORTC (C3, C2, C1, C0) on the ARM7TDMI can be used as interrupt sources. Only the PORTC register enables, configures, and services the interrupts.
  • Page 54 H a r d w a r e I n t e r r u p t s N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 55 B B u s M o d u l e BBus Module his chapter describes the BBus module, which provides the data path between NS7520 internal modules. Additional BBus functionality includes: Address and multiplexing logic that supports the data flow through the NS7520.

  • Page 56: Bbus Masters And Slaves

    B B u s m a s t e r s a n d s l a v e s BBus masters and slaves The BBus module consists of bus master and bus slave modules. The BBus state machine allows each bus master to control the bus in a round-robin manner. If a bus master does not require the bus resources when its turn comes around, that bus is skipped until the next round-robin slot.

  • Page 57: Address Decoding

    B B u s M o d u l e Address decoding The CPU address map is divided to allow access to the internal modules and external resources routed through the internal peripherals. Each slave module is given a small portion of the system address map for configuration and status.
  • Page 58 A d d r e s s d e c o d i n g N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 59 S Y S M o d u l e SYS Module he SYS module provides the NS7520 with its system clock and system (SYS_CLK) reset resources. (SYS_RESET) w w w . d i g i e m b e d d e d . c o m...

  • Page 60: Signal Description

    S i g n a l d e s c r i p t i o n Signal description The system control signals determine the basic operation of the chip: Signal mnemonic Signal name Description {XTALA1, XTALA2} Clock source Operate in one of two ways: The signals are affixed with a 10-20 MHz parallel mode quartz crystal or crystal oscillator and the appropriate components...

  • Page 61: System Clock Generation (Ns7520 Clock Module)

    S Y S M o d u l e controller, must be set as shown in "External oscillator {PLLTST_, BISTEN_, SCANEN_} mode hardware configuration," beginning on page 50. System clock generation (NS7520 clock module) The NS7520 clock module creates the BCLK and FXTAL signals. Both signals are used internally, but BCLK can also be accessed at ball A6 by setting the BCLKD field in the System Control register to 0 (see "System Control register,"...

  • Page 62: Ns7520 Clock Module Block Diagram

    U s i n g t h e e x t e r n a l o s c i l l a t o r NS7520 clock module block diagram This diagram provides an overview of the clock module. FXTAL External External...

  • Page 63: Using The Pll Circuit

    S Y S M o d u l e The clock module has two power pins: PLLVDD and PLLVSS. PLLVDD is connected to 1.5 volts PLLVSS is connected to ground The PLLTST* input is connected to ground to use boundary scan testing. It is connected to 3.3 volts through a 10K resistor to use the JTAG debugger.

  • Page 64: Pll Mode Hardware Configuration

    U s i n g t h e P L L c i r c u i t PLL mode hardware configuration Figure 5, "PLL mode hardware configuration," on page 53, shows how the crystal is connected to the XTALA1 and XTALA2 inputs. When the clock module is configured to use the PLL, the power to the module must be cleaner than when using an external oscillator.
  • Page 65 S Y S M o d u l e XTALA1 (K14) XTALA2 (K12) 1.5V PLLVDD (L15) PLLVSS (L12) BCLK The NS7520 address bus has internal pullups. FXTAL 2.7K pulldown resistors can be connected to the address lines to configure the PLL settings at bootup.

  • Page 66: Setting The Pll Frequency

    S e t t i n g t h e P L L f r e q u e n c y Setting the PLL frequency Three fields — IS (charge pump current), FS (output divider), and ND (PLL multiplier) — in the PLL Settings register control the behavior of the PLL circuit. You cannot write to the PLL Settings register directly, however;...
  • Page 67 S Y S M o d u l e Bits Access Mnemonic Reset Description D08:07 Read ‘b10 Charge pump current only Sets the PLL’s charge pump current. The IS field defaults to binary ‘b10 when address lines [8:7] are not pulled down on powerup. The IS value is based on the value in the ND field.
  • Page 68 S e t t i n g t h e P L L f r e q u e n c y A[8:7] A[6:5] A[4:0] ND+1 PLL Settings reg Notes 23.0 10000 00101 0x00000084 27.6 10001 00110 0x00000085 32.3 10010 00111 0x00000086 36.9...

  • Page 69: Register

    S Y S M o d u l e Notes: Digi guarantees that the NS7520B-1-C36 will work at all frequencies up to 36.9MHz. Digi guarantees that the NS7520B-1-C46 will work at all frequencies up to 46.1MHz. Digi guarantees that the Ns7520B-1-C55 will work at all frequencies up to 55.3MHz.
  • Page 70 S e t t i n g t h e P L L f r e q u e n c y PLL frequency. The NS7520 resets whenever the PLLCNT field is changed, then starts running at the new frequency dictated by the PLLCNT value. The readback value is not valid until software has performed a write to this register.

  • Page 71: Reset Circuit Sources

    S Y S M o d u l e Digi guarantees that the NS7520B-1-C36 will work at all frequencies up to 36.9MHz. Digi guarantees that the NS7520B-1-C46 will work at all frequencies up to 46.1MHz. Digi guarantees that the Ns7520B-1-C55 will work at all frequencies up to 55.3MHz.
  • Page 72 N S 7 5 2 0 b o o t s t r a p i n i t i a l i z a t i o n Address bit Name Description ADDR[27] Endian configuration Little Endian configuration Big Endian configuration ADDR[26] CPU bootstrap CPU disabled;...
  • Page 73 G E N M o d u l e GEN Module The GEN module provides the NS7520 with its main system control functions, as well as the following: Two programmable timers with interrupt One programmable bus-error timer One programmable watchdog timer Two 8-bit programmable general-purpose I/O ports w w w .

  • Page 74: Module Configuration

    M o d u l e c o n f i g u r a t i o n Module configuration The GEN module is configured as shown: Address Register FFB0 0000 System Control register FFB0 0004 System Status register FFB0 000C Software Service register FFB0 0010...

  • Page 75: Gen Module Registers

    G E N M o d u l e GEN module registers All registers are 32 bits unless otherwise noted. System Control register Address: FFB0 0000 General information All bits in the System Control register are active high unless an underscore (_) appears in the signal name;...
  • Page 76 G E N m o d u l e r e g i s t e r s Bits Access Mnemonic Reset Description Software watchdog enable Set to 1 to enable the watchdog timer circuit.The watchdog timer can be configured, using SWRI, to generate an interrupt or reset condition if and when the watchdog timer expires.
  • Page 77 G E N M o d u l e Bits Access Mnemonic Reset Description D17:16 Bus monitor timer Controls the timeout period for the bus monitor timer: 128 BCLKs (bus clocks) 64 BCLKS 32 BCLKS 16 BCLKS The BMT field generally is set to its maximum value, but can be set to a lower value to minimize the latency when issuing a data abort signal.
  • Page 78 G E N m o d u l e r e g i s t e r s Bits Access Mnemonic Reset Description DMATST DMA module test mode Resets the DMA controller subsystem. Also allows the ARM processor direct access to the internal context RAM found in the DMA controller.
  • Page 79 G E N M o d u l e Bits Access Mnemonic Reset Description D05:04 BSYNC TA_ input synchronizer Defines the level of synchronization performed within the NS7520 for TA_ input: 1-stage synchronizer 1-stage synchronizer 2-stage synchronizer Do not use this setting The NS7520 can process the TA_ input signal using a 1- stage flip-flop synchronizer or a 2-stage synchronizer.

  • Page 80: System Status Register

    G E N m o d u l e r e g i s t e r s System Status register Address: FFB0 0004 All bits in the System Status register, except EXT, WDOG, PLL, and SOFT, are loaded during a hardware reset only. EXT, WDOG, PLL, and SOFT are loaded during any reset.

  • Page 81: Software Service Register

    G E N M o d u l e Bits Access Mnemonic Reset Description WDOG Last reset caused by watchdog timer When set to 1, indicates that a watchdog timeout occurred and generated an internal hardware reset condition. Note: Because the RESET_ pin is not asserted, this reset does not initialize internal parameters as described in "NS7520 bootstrap initialization"...

  • Page 82: Timer Control Registers

    G E N m o d u l e r e g i s t e r s The Software Service register (SWSR) acknowledges the system watchdog timer. To do so, firmware must write to the register using two separate write ‘h5A ‘hA5 operations.
  • Page 83 G E N M o d u l e TIMEOUT = [4096 * (TC + 1)] / F TCLK = 0; TPRE = 1 XTALE TIMEOUT = (TC + 1) / F TCLK = 1; TPRE = x SYSCLK TIRO TPRE TCLK Register bit definition...
  • Page 84 G E N m o d u l e r e g i s t e r s Bits Access Mnemonic Reset Description TCLK Timer clock source Use F as timer clock source XTALE Use F as timer clock source SYSCLK Selects the reference clock for the timer module.

  • Page 85: Timer Status Registers

    G E N M o d u l e Timer Status registers Address: FFB0 0014 / FFB0 001C Rsvd Reserved TCLK Register bit assignment Bits Access Mnemonic Reset Description Reserved Timer interrupt pending Set to 1 when the timer is enabled and the CTC value counts down to 0.
  • Page 86 G E N m o d u l e r e g i s t e r s The PORTA register configures the PORTA general-purpose input/output (GPIO) pins. Each of the PORTA GPIO pins can be individually programmed — as general-purpose input or output, or special function input or output —...
  • Page 87 G E N M o d u l e Bits Access Mnemonic Reset Description D07:00 ADATA PORTA data register Used when a PORTA bit is configured to operate in GPIO mode. Reading the ADATA field provides the current state of the GPIO signal, regardless of its configuration mode.
  • Page 88 G E N m o d u l e r e g i s t e r s PORTA AMODE=0 AMODE=1 ADIR=0 ADIR=1 ADIR=0 ADIR=1 PORTA1 GPIO IN GPIO OUT SER1_CTS DONE1_OUT_ PORTA0 GPIO IN GPIO OUT SER1_SPI_S_ENABLE_ SER1_SPI_M_ENABLE_ OUT/SER1_OUT2 IN/SER1_DCD_/ DONE1_IN_/ SER1_TXC IN...

  • Page 89: Portc Configuration Register

    G E N M o d u l e PORTC Configuration register Address: FFB0 0028 The PORTC register configures the PORTC general-purpose input/output (GPIO pins). Each of the PORTC GPIO pins can be individually programmed — as general-purpose input or output, or special function input or output — as applicable. Table 31 describes the PORTC register;...
  • Page 90 G E N m o d u l e r e g i s t e r s Bits Access Mnemonic Reset Description D07:00 CDATA PORTC data register Used when a PORTC bit is configured to operate in GPIO mode. Reading the CDATA field provides the current state of the GPIO signal, regardless of its configuration mode.
  • Page 91 G E N M o d u l e PORTC CSF=0 CMODE=0 CMODE=1 CDIR=0 CDIR=1 CDIR=0 CDIR=1 PORTC0 GPIO IN GPIO OUT LEVELIRQ0=CDIR0 PORTC CSF=1 CMODE=0 CMODE=1 CDIR=0 CDIR=1 CDIR=0 CDIR=1 PORTC7 SER2_TXD PORTC6 DREQ2_IN SER2_DTR_ PORTC5 REJECT_ SER2_RTS_ PORTC4 SER2_SPI_S_CLK IN/ SER2_SPI_M_CLK SER2_RXC IN...

  • Page 92: Interrupts

    I n t e r r u p t s READBACK When reading the CDATA field, the data read depends on how the pin is configured: Configured as GPIO output. Reads data from the register whose data drives the pin. This can, for example, mask a short circuit on the output pin. All other configurations.

  • Page 93: Interrupt Controller Registers

    G E N M o d u l e Interrupts come from different sources on the chip and are managed with Interrupt Control registers. Interrupts can be enabled/disabled on a per-source basis using the Interrupt Enable registers. These registers serve as masks for the different interrupt sources.
  • Page 94 I n t e r r u p t s Bits Access Mnemonic Reset Description D31:19 DMA1–13 The DMA1 through DMA13 bit positions correspond to interrupts sourced by DMA channel 1 through 13. Reserved ENET1RX The ENET1RX bit position corresponds to an interrupt sourced by the Ethernet receiver.
  • Page 95 G E N M o d u l e w w w . d i g i e m b e d d e d . c o m...
  • Page 96 I n t e r r u p t s N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 97 M e m o r y C o n t r o l l e r M o d u l e Memory Controller Module he memory (MEM) module provides a glueless interface to external memory devices such as flash, DRAM, and EEPROM. The memory controller contains an integrated DRAM controller, and supports five unique chip select configurations.

  • Page 98: About The Mem Module

    A b o u t t h e M E M m o d u l e About the MEM module The MEM module monitors the BBus interface for access to the BUS module; that is, any access not addressing internal resources. If the BBus for the access corresponds to a Base Address register in the MEM module, the module provides the memory access signals and responds to the BBus with the appropriate completion signal.

  • Page 99: Mem Module Configuration

    M e m o r y C o n t r o l l e r M o d u l e Chip select configured for SRAM. The MEM module controls the CS[4:0]_, OE_, and WE_ signals. The address from the current bus master is driven directly to A[27:0].

  • Page 100: Setting The Chip Select Address Range

    M E M m o d u l e c o n f i g u r a t i o n Address Mnemonic Register FFC0 0000 MMCR Memory Module Configuration register FFC0 0010 BAR0 Chip Select 0 Base Address register FFC0 0014 OR0A Chip Select 0 Option Register A...

  • Page 101: Memory Module Configuration Register

    M e m o r y C o n t r o l l e r M o d u l e A 0 in the MASK field indicates that the associated address is to be ignored in the address decoding process. When accessing a static memory device, the maximum value of the base Note: address is...
  • Page 102 M E M m o d u l e c o n f i g u r a t i o n The software reset command issued by the GEN module Software Service Note: register has no effect on any MEM Module Configuration registers. AMUX RFCNT REFEN...
  • Page 103 M e m o r y C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description AMUX Enable external address multiplexing Disable external address multiplexing on PORTA2 for all DRAM banks Enable external address multiplexing on PORTA2 for all DRAM banks Controls whether the NS7520 uses its internal...

  • Page 104: Chip Select Base Address Register

    M E M m o d u l e c o n f i g u r a t i o n Bits Access Mnemonic Reset Description AMUX2 Internal/External/RAS/CAS mux Normal operation Drive the DRAM MUX control out PORTA2, regardless of the AMUX and DMUXS settings Used to drive the DRAM RAS/CAS address multiplexing control signal out the PORTA2 pin, regardless of the AMUX setting.
  • Page 105 M e m o r y C o n t r o l l e r M o d u l e BASE DMUX DMUX BASE PGSIZE DMODE EXTTA IDLE BURST Bits Access Mnemonic Reset Description D31:12 BASE Base address Determines the physical base address of the memory peripheral chip select.
  • Page 106 M E M m o d u l e c o n f i g u r a t i o n Bits Access Mnemonic Reset Description D09:08 DMODE DRAM configuration mode FP DRAM EDO DRAM SDRAM Reserved Controls the DRAM type when the memory device is configured to operate in DRAM mode.
  • Page 107 M e m o r y C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description DMUXM DRAM internal address multiplexer mode 10 CAS 8 CAS Controls which DRAM address multiplexing style is used for this DRAM memory peripheral.
  • Page 108 M E M m o d u l e c o n f i g u r a t i o n Bits Access Mnemonic Reset Description Valid bit Enables the chip select. When set to 1, the memory controller uses the fields in the Chip Select Base Address and Chip Select Option registers to control the behavior of the peripheral memory cycles.

  • Page 109: Chip Select Option Register A

    M e m o r y C o n t r o l l e r M o d u l e Chip Select Option Register A Address: FFC0 0014/24/34/44/54 The Chip Select Option Register A defines the physical size of the chip select, as well as other features.
  • Page 110 M E M m o d u l e c o n f i g u r a t i o n Bits Access Mnemonic Reset Description WAIT[3:0]/BCYC[1:0] continued For OE- or WE-controlled cycles, an additional BCLK cycle is added to each memory cycle. When DRSEL=0 CS[4:0]_ is asserted for WAIT+2 BCLK cycles in a single access.
  • Page 111 M e m o r y C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description WAIT[3:0]/BCYC[1:0] continued The first memory cycle of a burst access follows the timing of a single access. CAS_ is asserted BCYC BCLK cycles for all cycles that follow the initial cycle in a burst.
  • Page 112 M E M m o d u l e c o n f i g u r a t i o n Bits Access Mnemonic Reset Description OE CTRL_ Read cycle mode Operate in OE controlled mode; the memory peripheral operates in a mode in which the OE_ signal is asserted after, and negated while, CS[4:0]_ is asserted.

  • Page 113: Chip Select Option Register B

    M e m o r y C o n t r o l l e r M o d u l e Chip Select Option Register B Address: FFC0 0018/28/38/48/58 Reserved Reserved WAIT[5:4] BCYC[3:2] SYNC Bits Access Mnemonic Reset Description D31:06 Reserved D05:04...

  • Page 114: Static Memory (Sram) Controller

    S t a t i c m e m o r y ( S R A M ) c o n t r o l l e r Bits Access Mnemonic Reset Description D01:00 SYNC TA_ input synchronizer Reserved 1-stage synchronizer 2-stage synchronizer Reserved Defines the level of synchronization performed...
  • Page 115 M e m o r y C o n t r o l l e r M o d u l e BCLK ADDR BEn_ CS0_ CS1_ R/W_ DATA Sync Write Sync Read Sync Write Sync Write Figure 6: Synchronous SRAM cycles All outputs change state relative to the rising edge of BCLK with the exception of OE_ and WE_, which transition on the falling edge of BCLK.

  • Page 116: Burst Cycles

    S t a t i c m e m o r y ( S R A M ) c o n t r o l l e r BCLK ADDR BEn_ CS0_ CS1_ R/W_ DATA Async Write Async Read Async Write Figure 7: Asynchronous SRAM cycles The BE_, OE_, and WE_ signals transition based on the falling edge of BCLK.

  • Page 117: Ns7520 Dram Address Multiplexing

    M e m o r y C o n t r o l l e r M o d u l e BCLK ADDR[31:4] ADDR[3:1] R/W_ BE0_ BE1_ DATA Figure 8: SRAM synchronous burst read cycle NS7520 DRAM address multiplexing The NS7520 can be configured to use an internal DRAM address multiplexer or an external address multiplexer.
  • Page 118 N S 7 5 2 0 D R A M a d d r e s s m u l t i p l e x i n g When a particular DRAM has less than 14 address bits, use the lower order NS7520 address bits and leave the upper NS7520 address bits disconnected.
  • Page 119 M e m o r y C o n t r o l l e r M o d u l e NS7520 multiplexed address outputs NS7520 pin DRAM pin 8-bit DRAM peripheral (20 address bits: 10 RAS and 10 CAS) NS7520 pin DRAM pin 16-bit DRAM peripheral (20 address bits: 10 RAS and 10 CAS)

  • Page 120: Using The External Multiplexer

    N S 7 5 2 0 D R A M a d d r e s s m u l t i p l e x i n g NS7520 multiplexed address outputs NS7520 DRAM 16-bit DRAM peripheral (22 address bits: 14 RAS and 8 CAS) NS7520 DRAM 32-bit DRAM peripheral (22 address bits: 14 RAS and 8 CAS)

  • Page 121: Dram Refresh

    M e m o r y C o n t r o l l e r M o d u l e Setting the DMUXS bit indicates that the internal address multiplexer must be disabled when the specific chip select is activated. The NS7520 drives the address bus using standard addressing without any multiplexing, but only for the specific chip select, the internal address multiplexer is disabled, and the multiplexer indicator is driven out the PORTA2 pin.

  • Page 122: Single Cycle Read/Write

    F P / E D O D R A M c o n t r o l l e r Normal and burst (FP/EDO) cycles Programmable wait states for normal (also first cycle ion burst access) and burst cycles Programmable base address and chip select size Single cycle read/write Figure 9 shows FP DRAM normal read and write cycles.

  • Page 123: Fp/Edo Dram Burst Cycles

    M e m o r y C o n t r o l l e r M o d u l e FP/EDO DRAM burst cycles The DRAM controller supports both read and write burst cycles. A DRAM Burst cycle must operate with a minimum of one wait state for the first cycle and a minimum of two BCLK cycles in subsequent cycles.

  • Page 124: Ns7520 Sdram Interconnect

    S D R A M NS7520 SDRAM interconnect The NS7520 can interconnect to standard 16Mb and 64Mb SDRAM components, using x32, x16, and x8 SDRAM configuration. You can use 128Mb components in the x32 configuration, but not in the x8 or x16 configurations.
  • Page 125 M e m o r y C o n t r o l l e r M o d u l e 2x16M SDRAM signal components 1x32 SDRAM component NS7520 signal 16 Mb (1Mx16) 64Mb (4Mx16) 64Mb (2Mx32) 128Mb (4Mx32) BCLK D31-D16 D15-D00 - Device 1...
  • Page 126 S D R A M NS7520 signal 16M SDRAM signal 64M SDRAM signal CS/RAS_ CS[4:0]_ CS[4:0]_ CAS3_ RAS_ RAS_ CAS2_ CAS_ CAS_ CAS1_ CAS0_ A10/AP A10/AP BE3_ UDQM_ UDQM_ BE2_ LDQM_ LDQM_ BE1_ BE0_ Table 43: x16 SDRAM interconnect 1 1 4 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 127 M e m o r y C o n t r o l l e r M o d u l e NS7520 signal 16M SDRAM signal 64M SDRAM signal BCLK D31-D16 D15-D00 D15-D00 Table 43: x16 SDRAM interconnect x8 SDRAM configurations Table 44 identifies the interconnect between the NS7520 and SDRAM when SDRAM is used in an x8 configuration.

  • Page 128: Sdram A10/Ap Support

    S D R A M NS7520 signal 16M SDRAM signal 64M SDRAM signal BCLK D31-D16 D15-00 D15-00 Table 44: x8 SDRAM interconnect SDRAM A10/AP support The SDRAM A10/AP signal multiplexes one of the RAS signals with an auto-precharge command indicator. During the active command, the A10/AP signal must provide the DRAM A10 logical RAS address value.

  • Page 129: Command Definitions

    M e m o r y C o n t r o l l e r M o d u l e The NS7520 provides the A10/AP multiplexing function using the CAS0_ pin. During the active command, the CAS0_ pin is driven with the logical value of one of the address bits A[21:18] as a function of the port size configuration defined in Chip Select Option Register A and the mux mode defined in the Chip Select Base Address register.

  • Page 130: Memory Timing Fields - Sdram

    S D R A M Command CSx_ A13:0 CAS3_ RAS# CAS2_ CAS# CAS1_ WE# CAS0_ A10/AP Load mode Op-code Table 45: SDRAM command definitions Memory timing fields — SDRAM The WAIT configuration in the Chip Select Option register provides the SDRAM T and T parameters.

  • Page 131: Sdram Mode Register

    M e m o r y C o n t r o l l e r M o d u l e BSIZE Burst length Full page The JEDEC SDRAM standard requires the SDRAM load mode command to set burst length to to recognize burst terminate commands.

  • Page 132: Sdram Read Cycles

    S D R A M SDRAM read cycles Figure 11 and Figure 12 provide timing examples for SDRAM normal and burst reads, respectively, with WAIT and BCYC configured with a value of 0. precharge activate read bstop BCLK BE[3:0] D[31:0] CS[7:0]_ One Valid Per Cycle CAS3_(RAS_)
  • Page 133 M e m o r y C o n t r o l l e r M o d u l e read bstop inhibit BCLK BE[3:0] D[31:0] CS[7:0]_ One Valid Per Cy cle CAS3_(RAS_) CAS2_(CAS_) CAS1_(WE_) A[13:0] AMUX TA_ {output} TEA_(LAST_) {output} TA_ {input} TEA_(LAST_) {input}...

  • Page 134: Sdram Write Cycles

    S D R A M wait states are inserted after the read command, depending on the value of the BCYC configuration. The BCYC configuration identifies the CAS latency specification for the SDRAM. The burst stop command is issued at the end of the current burst read operation.
  • Page 135 M e m o r y C o n t r o l l e r M o d u l e write write write write in hi bi t BCLK BE[3:0] D[31:0] CS[7:0]_ One Valid Per Cy cle CAS3_(RAS_) CAS2_(CAS_) CAS1_(WE_) A[13:0]...

  • Page 136: Peripheral Page Burst Size

    P e r i p h e r a l p a g e b u r s t s i z e The write command is always issued during the T2 state since data is available only at that time. If the precharge and active commands are not required, a NOP is inserted in the T1 state of the write cycle.
  • Page 137 M e m o r y C o n t r o l l e r M o d u l e The memory controller does a normal access to address using the WAIT field to ’hC determine access timing. The memory controller then follows with 3 burst beats to address offsets , and using the BCYC field to determine the access timing.
  • Page 138 P e r i p h e r a l p a g e b u r s t s i z e 1 2 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 139 D M A M o d u l e DMA Module he NS7520 supports 13 DMA channels. Each channel moves blocks of data between memory and a memory peripheral. Each block transfer is defined by a descriptor of two words (memory-to-peripheral) or three words (memory-to-memory) in circular buffers maintained by the CPU.

  • Page 140: Dma Module

    D M A m o d u l e DMA module Each DMA controller has a state machine and a block of static RAM referred to as context RAM. The context RAM contains the current state of each DMA channel. The single state machine supports all DMA channels in parallel, by context switching from channel to channel.

  • Page 141: Memory-To-Memory Operation

    D M A M o d u l e not touch this data; rather, it controls the flow of data through the BBus and provides the external address for a single data transfer operation. Figure 16 provides a simple representation of DMA fly-by mode: Memory Address channel...

  • Page 142: Dma Buffer Descriptor

    D M A b u f f e r d e s c r i p t o r DMA buffer descriptor All DMA channels operate using a buffer descriptor. Each DMA channel remains idle until enabled using the CE bit in the DMA Control register (see "DMA Control register," beginning on page 136).
  • Page 143 D M A M o d u l e Buffer descriptor bit definitions Description Wrap bit. When set (W=1), tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors. The next buffer descriptor is found using the initial DMA channel buffer descriptor pointer.

  • Page 144: Dma Channel Assignments

    D M A c h a n n e l a s s i g n m e n t s Buffer descriptor field definitions Field Description Source buffer pointer/Buffer The source buffer pointer field identifies the starting location of the data pointer buffer.

  • Page 145: Dma Channel Registers

    D M A M o d u l e FB write indicates fly-by peripheral-to-memory. FB read indicates fly-by memory-to-peripheral. MM indicates memory-to-memory. DMA channels 3/5 and 4/6 can interface with external peripheral devices using DMA handshake signals multiplexed through the GPIO pins in PORTA and PORTC.
  • Page 146 D M A c h a n n e l r e g i s t e r s The DMA Control register should be written to enable the DMA channel only after all other registers and descriptors are valid. Address Description FF90 0000...
  • Page 147 D M A M o d u l e Address Description FF90 00114 DMA 6 Status register FF90 0120 DMA 7 Buffer Descriptor Pointer register FF90 0130 DMA 7 Control register FF90 0134 DMA 7 Status register FF90 0140 DMA 8 Buffer Descriptor Pointer register FF90 0150 DMA 8 Control register FF90 0154...

  • Page 148: Buffer Descriptor Pointer Register

    D M A c h a n n e l r e g i s t e r s Buffer Descriptor Pointer register Address: FF90 0000 / 20 / 40 / 60 / 80 / A0 / C0 / E0 / 100 / 120 / 140 / 160 / 180 / 1A0 / 1C0 / 1E0 The Buffer Descriptor Pointer register contains the address of the first buffer descriptor in a contiguous list of descriptors.
  • Page 149 D M A M o d u l e Bits Access Mnemonic Reset Description Channel abort request When set, causes the current DMA operation to complete and the buffer to be closed. CA is not cleared automatically after the requested abort is complete; firmware must clear the bit after recognizing CAIP active.
  • Page 150 D M A c h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description D25:24 Burst transfer enable Determines whether the DMA channel can use burst transfers through the bus. This configuration applies to both buffer descriptor and peripheral data access.
  • Page 151 D M A M o d u l e Bits Access Mnemonic Reset Description BTE continued The DMA delivers to the destination peripheral the same number of bytes read from the source peripheral, regardless of whether the destination peripheral can support bursting. If the destination peripheral cannot support bursting, the DMA controller issues multiple bus cycles to complete the data move.
  • Page 152 D M A c h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description REQ continued DMA channels 4/6 interface with an external peripheral using handshaking signals multiplexed through PORTC. When REQ is set to 0 in DMA channel 4 and set to 1 in DMA channel 6, DMA channel 6 is tied to the external DMA port through PORTC.
  • Page 153 D M A M o d u l e Bits Access Mnemonic Reset Description D17:16 SIZE Data operand size 32 bit 16 bit 8 bit Reserved Used to define the size of each DMA transaction when the DMA controller is configured for external request mode (DMA channel 3 only) or memory-to-memory DMA mode.

  • Page 154: Dma Status/Interrupt Enable Register

    D M A c h a n n e l r e g i s t e r s DMA Status/Interrupt Enable register Address: FF90 0014 / 34 / 54 / 74 / 94 / B4 / D4 / F4 / 114 / 134 / 154 / 174 / 194 / 1B4 / 1D4 / 1F4 The interrupt enable (IE) bits can be set to cause an interrupt to occur when the corresponding interrupt status bit is set in the DMA Status register.
  • Page 155 D M A M o d u l e Bits Access Mnemonic Reset Description NRIP Buffer not ready interrupt pending Set when the DMA channel encounters a buffer descriptor whose F bit is in the incorrect state. When NRIP is set, the DMA channel stops until the bit is cleared by firmware;...

  • Page 156: Ethernet Transfer Considerations

    E t h e r n e t t r a n s f e r c o n s i d e r a t i o n s Bits Access Mnemonic Reset Description CAIE Channel abort interrupt enable Use these bits to enable interrupts to be generated when the associated IP bits are set.

  • Page 157: Ethernet Transmitter Considerations

    D M A M o d u l e In general, the problem of transmit underruns can be avoided by running in half duplex rather than full duplex. Late collisions can be eliminated by proper network design; late collisions are caused by too many cascaded levels of hubs, switches, repeaters, and the like.

  • Page 158: External Peripheral Dma Support

    E x t e r n a l p e r i p h e r a l D M A s u p p o r t Because interrupts are set when DMA channel 1 encounters buffers that are not ready, the device driver should be designed with the smallest buffers in the A pool and the largest buffers in the D pool.

  • Page 159: Signal Description

    D M A M o d u l e Signal description Signal Description DREQ_ An input to the NS7520, sourced by the external device. All transfers are initiated when the external device asserts DREQ_ low. When the external device wants a DMA transfer (either read or write), it asserts the DREQ_ signal.

  • Page 160: Dma Controller Reset

    D M A c o n t r o l l e r r e s e t NS7520 External device DREQ_ DREQ_ DACK_ Enable DONE_ DONE R/W_ Direction DATA[31:0] DATA[31:0] ADDR[27:0] ADDR[27:0] CSx_ CSx_ Memory ADDR[X:0] DATA{ 31:0] R/W_ Figure 20: Hardware needed for external memory-to-memory DMA transfers If the source buffer pointer points to the external device, the device, in conjunction with appropriate memory device timing or external bus cycle...
  • Page 161 E t h e r n e t M o d u l e Ethernet Module he Ethernet controller module provides the NS7520 with one IEEE 802.3u compatible Ethernet interface. Two modules comprise the Ethernet interface: the Ethernet front-end (EFE) and the media access controller (MAC). The MAC module interfaces to an external physical layer (PHY) device using the media independent interface (MII) standard defined by IEEE 802.3u.

  • Page 162: Ethernet Front-End (Efe)

    E t h e r n e t f r o n t - e n d ( E F E ) Ethernet front-end (EFE) Figure 21 shows a high-level block diagram of the EFE module. The EFE module provides the FIFO handling interface between the NS7520 BBus and MAC modules. MAC RX interface MAC TX interface byte...

  • Page 163: Transmit And Receive Fifos

    E t h e r n e t M o d u l e EFE logic provides all control and status registers required by the Ethernet module. The transmitter and receiver each provide a 16-bit status word after processing each Ethernet frame.

  • Page 164: Receive Buffer Descriptor Selection

    E t h e r n e t f r o n t - e n d ( E F E ) The MAC forwards good Ethernet packets through address filtering. Packets can be filtered based on station address, broadcast, and select multicast packets. Those packets that pass through address filtering are moved into system memory.

  • Page 165: External Cam Filtering

    E t h e r n e t M o d u l e Interrupts are set when the DMA channel encounters buffers that are not ready. The device driver should be designed with the smallest buffers in the A pool and the largest buffers in the D pool.

  • Page 166: Mac Module

    M A C m o d u l e MAC module The MAC component of the NS7520 provides a full function 10/100 Mbps media access controller module with media independent interface (MII) and optional interface modules, which include MII, PMD, and ENDEC. The basic features in the MAC module include: 10/100 Mbps Ethernet MAC MII interface...
  • Page 167 E t h e r n e t M o d u l e MAC core 10/100 Interface TFUN Host ENDEC RFUN HOST CLKRST MIIM Mgmt Figure 23: MAC block diagram Other modules in the diagram include: MAC core — 10/100 Mbps media access controller. Performs the CSMA/CD function and flow control functions.

  • Page 168: Dma Channel Assignments

    D M A c h a n n e l a s s i g n m e n t s DMA channel assignments One DMA channel is dedicated to Ethernet receive and one DMA channel is dedicated to Ethernet transmit. The Ethernet receiver has four DMA subchannels, which support the receive buffer descriptor selection feature (see "DMA buffer descriptor,"...
  • Page 169 E t h e r n e t M o d u l e Address Register Register description FF80 0414 MAXF Maximum Frame register FF80 0418 SUPP PHY Support register FF80 041C TEST Test register FF80 0420 MCFG MII Management Configuration register FF80 0424 MCMD MII Management Command register...

  • Page 170: Ethernet General Control Register (Egcr) Bit Definitions

    E F E c o n f i g u r a t i o n Ethernet General Control register (EGCR) bit definitions Address: FF80 0000 General information These fields should be set only once, on device open: ERXDMA ETXDMA ERXLNG ETXWM ERXSHT...
  • Page 171 E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description Enable receive FIFO Disables inbound data flow and resets the FIFO Enables inbound data flow Set to 1 to allow data to be received from the MAC receiver.
  • Page 172 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description Enable transmit FIFO Disables outbound data flow and resets the FIFO Enables outbound data flow Set to 1 to allow data to be written to the TX FIFO. Clear to reset the transmit side FIFO.
  • Page 173 E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description EFULLD Enable full-duplex operation Set to 1 to allow the Ethernet TX and RX DMA operations to operate simultaneously. This bit must be set when the Ethernet link negotiation results in full-duplex mode.
  • Page 174 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description MAC_RESET 0 MAC software reset Restore MAC to normal operation Reset MAC host interface ITXA Insert transmit source address When set, forces the MAC to automatically insert the Ethernet source MAC address into the Ethernet transmit packet.
  • Page 175 E t h e r n e t M o d u l e MODE field Output based on EFE CSR bit Not ‘b00 TXD1=PDN inverted, open drain Not ‘b00 TXD2=AUI_TP[1] Not ‘b00 TXD3=AUI_TP[0] Not ‘b00 TXER=LNK_DIS_ Not ‘b00 and not ‘b11 MDC=LPBK ‘b11 MDC=LPBK inverted...

  • Page 176: Ethernet General Status Register (Egsr) Bit Definitions

    E F E c o n f i g u r a t i o n Ethernet General Status register (EGSR) bit definitions Address: FF80 0004 General information These fields are used only when using Ethernet receive in interrupt service mode rather than DMA mode (DMA interface logic).
  • Page 177 E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description D29:28 RXFDB Receive FIFO data available Valid only when RXREGR (D27) = 1. Full-word One byte Half-word Three bytes; LENDIAN determines which three Must be used in conjunction with RXREGR.
  • Page 178 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description D23:20 Reserved TXREGE Transmit register empty Set to 1 whenever the transmit FIFO is ready to accept data. When active high, this bit can cause an interrupt when the ETXREGE bit is also set (in the Ethernet General Control register).

  • Page 179: Ethernet Fifo Data Register

    E t h e r n e t M o d u l e Data bit NS7520 pin RXD2 RXD1 RXD3 RXER RXDV Table 56: ENDEC status signal cross-reference Ethernet FIFO Data register Address: FF80 0008 / FF80 000C (secondary address) The Ethernet FIFO Data register allows manual interface with the Ethernet FIFO, rather than using DMA support.

  • Page 180: Ethernet Transmit Status Register

    E F E c o n f i g u r a t i o n The Ethernet Receive Status register (see "Ethernet Receive Status Note: register" on page 173) should be read before clearing the RXBR bit. When operating in interrupt service mode, RXBR is cleared manually. When operating in DMA mode, the Ethernet Receive Status register is read automatically and RXBR is cleared automatically.
  • Page 181 E t h e r n e t M o d u l e General Status register when a transmit frame is completed and the Ethernet Transmit Status register is loaded. The lower 16 bits (D15:00) of the register are also loaded into the StatusOrIndex field of the DMA buffer descriptor when using DMA mode.
  • Page 182 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description TXAL Transmit abort — late collision Set to 1 to indicate that the last Ethernet packet was not transmitted successfully; packet transmission was aborted due to a late collision problem.
  • Page 183 E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description TXAUR Transmit aborted — underrun Set to 1 to indicate that the last Ethernet packet was not transmitted successfully; packet transmission was aborted due to a FIFO underrun condition.
  • Page 184 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description TXDEF Transmit packet deferred Set to 1 to indicate that the last successfully transmitted Ethernet packet encountered a deferral. Transmission was delayed because the Ethernet medium was busy when trying to send the first transmission.

  • Page 185: Ethernet Receive Status Register

    E t h e r n e t M o d u l e Ethernet Receive Status register Address: FF80 0014 The Ethernet Receive Status register contains the status for the last completed receive buffer. The receive buffer complete bit (RXBR) is set in the Ethernet General Status register when a receive frame is completed and the Receive Status register is loaded.
  • Page 186 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description RXDV Receive data violation event previously seen Set to 1 to indicate that, at some point since the last recorded receive packet, a receive data violation was detected, noted, and reported with this receive packet event.
  • Page 187 E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description RXCRC Receive packet has CRC error Set to 1 to indicate that the next packet in the receive FIFO was received with a CRC error. When this bit is set, the RXREGR and RXFIFOH bits in the Ethernet General Status register remain inactive.

  • Page 188: Mac Configuration Register 1

    E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description ROVER Receive overflow Set to 1 to indicate that a receive FIFO overrun condition has occurred. An overrun condition occurs when the FIFO becomes full while receiving an Ethernet packet.
  • Page 189 E t h e r n e t M o d u l e Register bit assignment Bits Access Mnemonic Reset Description D31:16 Reserved SRST Soft reset Must be set before/while changing any other MAC bits, and cleared after they are modified. Setting this bit puts all MAC modules within the MAC block into reset mode, with the exception of the host interface.

  • Page 190: Mac Configuration Register 2

    E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description RXFLOW RX flow control The MAC acts on received PAUSE flow control frames. The MAC ignores all PAUSE flow control frames. PALLRX Pass ALL receive frames The MAC receiver indicates PASS CURRENT...
  • Page 191 E t h e r n e t M o d u l e Register bit assignment Bits Access Mnemonic Reset Description D31:15 Reserved EDEFER Excess Deferral Allows the MAC to defer to carrier indefinitely, per the 802.3u standard. The MAC aborts when the excessive deferral limit is reached.
  • Page 192 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description AUTOP Auto detect pad enable When set to 1, the MAC automatically detects the frame type — tagged or untagged — by comparing the two octets following the source address with ’h8100 VLAN protocol...
  • Page 193 E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description FLENC Frame length checking When set to 1, both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length, the check is performed.

  • Page 194: Back-To-Back Inter-Packet-Gap Register

    E F E c o n f i g u r a t i o n Back-to-Back Inter-Packet-Gap register Address: FF80 0408 Reserved Reserved IPGT Register bit assignment Bits Access Mnemonic Reset Description D31:07 Reserved D06:00 IPGT Back-to-back inter-packet-gap A programmable field that represents the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next packet.

  • Page 195: Non-Back-To-Back Inter-Packet-Gap Register

    E t h e r n e t M o d u l e Non-Back-to-Back Inter-Packet-Gap register Address: FF80 040C Reserved Rsvd IPGR1 Rsvd IPGR2 Register bit assignment Bits Access Mnemonic Reset Description D31:15 Reserved D14:08 IPGR1 Non back-to-back inter-packet-gap — part 1 A programmable field that represents the optional carrierSense window (referenced in IEEE 802.3 “Carrier Deference”).

  • Page 196: Collision Window/Collision Retry Register

    E F E c o n f i g u r a t i o n Collision Window/Collision Retry register Address: FF80 0410 Reserved Reserved CWIN Reserved RETX Register bit assignment Bits Access Mnemonic Reset Description D31:14 Reserved D13:08 CWIN Collision window ’h37 (55d)

  • Page 197: Maximum Frame Register

    E t h e r n e t M o d u l e Maximum Frame register Address: FF80 0414 Register bit assignment Reserved MAXF Bits Access Mnemonic Reset Description D31:16 Reserved D15:00 MAXF Maximum frame length ’h 0600 Represents a maximum receive frame of 1536 octets (resets ).

  • Page 198: Phy Support Register

    E F E c o n f i g u r a t i o n PHY Support register Address: FF80 0418 Reserved DLINK JAB- Reserved FORCEQ Rsvd 100X CIPH MODE Register bit assignment Bits Access Mnemonic Reset Description D31:08 Reserved RPE100X Reset PE100X module...

  • Page 199: Test Register

    E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description Reserved JABBER Enable Jabber protection Jabber is the condition in which a transmitter is stuck on longer than 50 ms, preventing other stations from transmitting.
  • Page 200 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description TBACK Test backpressure Set this bit to 1 to have the MAC assert backpressure on the link; this allows preamble to be transmitted raising carrier sense.

  • Page 201: Mii Management Configuration Register

    E t h e r n e t M o d u l e MII Management Configuration register Address: FF80 0420 Reserved RMIIM Reserved CLKS SPRE SCANI Register bit assignment Bits Access Mnemonic Reset Description D31:16 Reserved RMIIM Reset MII management Set this bit to 1 to reset the MII management module.
  • Page 202 E F E c o n f i g u r a t i o n CLKS field SYS_CLK ratio 75 MHz example 12 MHz example SYS_CLK / 4 SYS_CLK / 4 SYS_CLK / 6 2.0 MHz SYS_CLK / 8 SYS_CLK / 10 SYS_CLK / 14 SYS_CLK / 20...

  • Page 203: Mii Management Command Register

    E t h e r n e t M o d u l e MII Management Command register Address: FF80 0424 Reserved Reserved SPRE READ Register bit assignment Bits Access Mnemonic Reset Description D31:02 Reserved SCAN Automatically scan for read data When this bit is set to 1, the MII management module performs read cycles continuously.

  • Page 204: Mii Management Address Register

    E F E c o n f i g u r a t i o n MII Management Address register Address: FF80 0428 Reserved Reserved DADR Reserved RADR Register bit assignment Bits Access Mnemonic Reset Description D31:13 Reserved D12:08 DADR MII PHY device address Represents the 5-bit PHY device address field for management cycles.

  • Page 205: Mii Management Write Data Register

    E t h e r n e t M o d u l e MII Management Write Data register Address: FF80 042C Reserved MII w rite data Register bit assignment Bits Access Mnemonic Reset Description D31:16 Reserved D15:00 MWTD MII write data When this register is written, an MII management write cycle is performed using the 16-bit data defined in the PHY Address register by the preconfigured PHY device and...

  • Page 206: Mii Management Read Data Register

    E F E c o n f i g u r a t i o n MII Management Read Data register Address: FF80 0430 Reserved MII read data Register bit assignment Bits Access Mnemonic Reset Description D31:16 Reserved D15:00 MRDD MII read data Provides read data following an MII management read cycle.

  • Page 207: Mii Management Indicators Register

    E t h e r n e t M o d u l e MII Management Indicators register Address: FF80 0434 Reserved Reserved SCAN BUSY VALID Register bit assignment Bits Access Mnemonic Reset Description D31:03 Reserved NVALID Read data not valid A 1 indicates that the MII management read cycle is not complete and read data is not yet valid.

  • Page 208: Smii Status Register

    E F E c o n f i g u r a t i o n SMII Status register Address: FF80 0438 Reserved JAB- DUP- Reserved CLASH LINK SPEED Register bit assignment Bits Access Mnemonic Reset Description D31:05 Reserved CLASH MAC-to-MAC with PHY A 1 indicates that MAC-to-MAC mode is selected, but a PHY is detected.
  • Page 209 E t h e r n e t M o d u l e Station Address Register 1 Address: FF80 0440 Reserved OCTET1 OCTET2 Bits Access Mnemonic Reset Description D31:16 Reserved D15:08 OCTET1 ’h00 Station address octet 1 Holds the first octet of the station address (bits 47:40). D07:00 OCTET2 ’h00...
  • Page 210 E F E c o n f i g u r a t i o n Bits Access Mnemonic Reset Description D07:00 OCTET4 Station address octet 4 ’h00 Holds the fourth octet of the station address (bits 23:16). Table 78: Station Address Register 2 bit definition Station Address Register 3 Address: FF80 0448 Reserved...

  • Page 211: Station Address Filter Register

    E t h e r n e t M o d u l e Station Address Filter register Address: FF80 05C0 Reserved Reserved BROAD Register bit assignment Bits Access Mnemonic Reset Description D31:04 Reserved Enable promiscuous mode (receive all packets) A 1 indicates promiscuous mode.

  • Page 212: Register Hash Table

    E F E c o n f i g u r a t i o n Register hash table The MAC receiver provides the station address logic (SAL) with a 6-bit CRC value. This value points to a bit position in the 64-bit multicast hash table. A receive packet is accepted if the current frame is a multicast frame and the 6-bit CRC addresses a bit in the hash table that is set to 1.
  • Page 213 E t h e r n e t M o d u l e Bits Access Mnemonic Reset Description D31:16 Reserved D15:00 CRC values 31–16 Table 82: HT2 bit definition Address: FF80 05D8 Reserved Bits Access Mnemonic Reset Description D31:16 Reserved D15:00 CRC values 47–32...
  • Page 214 E F E c o n f i g u r a t i o n Calculating hash table entries The C code in this section describes how to calculate the hash table entries based on 6-byte Ethernet destination addresses. static ETH_ADDRESS mca_address[MAX_MCA];...
  • Page 215 E t h e r n e t M o d u l e This routine creates a hash table based on the CRC values of the MAC addresses set up by eth_add_mca(). The CRC value of each MAC address is calculated and the lower six bits are used to generate a value between 0 and 64.
  • Page 216 E F E c o n f i g u r a t i o n none static void set_hash_bit (BYTE *table, int bit) int byte_index, bit_index; byte_index = bit >> 3; bit_index = bit & 7; table [byte_index] |= (1 << bit_index); Function: int calculate_hash_bit (BYTE *mca) Description: This routine calculates which bit in the CRC hash table needs...
  • Page 217 E t h e r n e t M o d u l e memcpy (copy_mca, mca, sizeof (copy_mca)); for (index = 0; index < 3’ index++) copy_mca [index] = SWAP16 (copy_mca [index]); mcap = copy mca; crc = 0xffffffffL; for (mca_word = 0;...
  • Page 218 E F E c o n f i g u r a t i o n 2 0 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 219 S e r i a l C o n t r o l l e r M o d u l e Serial Controller Module he NS7520 supports two independent universal asynchronous/synchronous receiver/transmitter channels. Each channel supports several modes, conditions, and formats.

  • Page 220: Supported Features

    S u p p o r t e d f e a t u r e s Supported features Each serial channel supports these features: Independent programmable bit-rate generator UART and SPI modes High speed data transfer x1 mode: 4 Mbps –...

  • Page 221: Bit-Rate Generator

    S e r i a l C o n t r o l l e r M o d u l e CTS, DSR, DCD, RI state change detection – Clock/Data encoding – – NRZB NRZI – – Manchester – Multi-drop capable Figure 24 shows the structure of the serial module.

  • Page 222: Serial Protocols

    S e r i a l p r o t o c o l s You can configure the bit-rate generator to use the external oscillator, the external clock input, or internal system timing as its timing reference. This allows for a wider range of possible bit-rates.

  • Page 223: Spi Mode

    S e r i a l C o n t r o l l e r M o d u l e Enable the transmitter using the CTS handshaking signal. In this mode, the transmitter cannot start a new UART data frame unless CTS is active. If CTS is dropped anywhere in the middle of a UART data frame, the current character is completed but the next character is stalled.

  • Page 224: Fifo Management

    S P I m o d e Information transfer is also qualified with an enable signal. The SPI enable signal must be active low for data transfer to occur, regardless of the SPI clock signal. The SPI enable function allows multiple slaves to be individually addressed in a multi-drop configuration.
  • Page 225 S e r i a l C o n t r o l l e r M o d u l e results in the character being transmitted first and being 0x44 0x11 transmitted last. Processor interrupts vs. DMA The transmit FIFO can be filled using processor interrupts or DMA. When using processor interrupts, the processor can write one long word (4 bytes) of data to the transmit FIFO when the TRDY bit in Serial Channel Status Register A is active high.
  • Page 226 S P I m o d e active high. This long word can have 1, 2, 3, or 4 bytes of valid data within the word. The number of valid bytes is determined by the bit encoding in the RXFDB field in Serial Channel Status Register A.
  • Page 227 S e r i a l C o n t r o l l e r M o d u l e number of bytes for transfer. The SPI master port simultaneously transmits and receives the same number of bytes. A single clock signal controls the transfer of information;...
  • Page 228 S P I m o d e Configure the character GAP timer, if you want. The character GAP timer terminates a DMA transfer if the time between the receipt of two characters exceeds a programmable interval. (See "Serial Channel 1, 2 Receive Character Gap Timer,"...
  • Page 229 S e r i a l C o n t r o l l e r M o d u l e Receives one byte of inbound data for each byte of transmit data sent. The SPI master receiver cannot receive more data that what is transmitted. When the SPI master receiver collects four bytes, those four bytes are written to the RX FIFO.
  • Page 230 S P I m o d e occur, regardless of the SPI clock signal. The SPI enable function allows for multiple slaves to be addressed individually during a multi-drop configuration. Signals The GEN module must be configured appropriately to allow the SPI interface signals to interface with the PORTA and PORTC GPIO pins (see "PORTA Configuration register"...
  • Page 231 S e r i a l C o n t r o l l e r M o d u l e RCGT: 1 to enable the character GAP timer – – MODE: 11 for slave mode BITORDR: user-defined – Configure Serial Channel Control Register A, as shown: CE: 1 for enable –...

  • Page 232: General-Purpose I/O Configurations

    G e n e r a l - p u r p o s e I / O c o n f i g u r a t i o n s residual bytes to the RX FIFO, the buffer and/or character GAP timers must be used.

  • Page 233: Serial Port Performance

    S e r i a l C o n t r o l l e r M o d u l e Serial port performance The serial ports have a finite performance limit on their ability to handle various serial protocols. Performance is limited by the speed of the SYSCLK operating the NS7520.
  • Page 234 C o n f i g u r a t i o n Address Register FFD0 004C Channel 2 Bit-Rate register FFD0 0050 Channel 2 FIFO Data register FFD0 0054 Channel 2 Receive Buffer Gap Timer FFD0 0058 Channel 2 Receive Character Gap Timer FFD0 005C Channel 2 Receive Match register FFD0 0060...

  • Page 235: Serial Channel Registers

    S e r i a l C o n t r o l l e r M o d u l e Serial Channel registers All control bits are active high unless followed by an underscore (_); the underscore indicates active low. Serial Channel 1, 2 Control Register A Address: FFD0 0000 / 40 STICK...
  • Page 236 S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description STICKP Stick parity Can be used to force the UART parity field to a certain state, as defined by the EPS field, instead of a parity bit calculated against the data word.
  • Page 237 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description RTSRX Enable active RTS (only when RX FIFO has space) Supports hardware handshaking. When RTSRX is set, the RTS output provides the receiver FIFO almost-full condition.
  • Page 238 S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description Request-to-send active Controls the state of the external request-to- send signal. Setting RTS to 1 causes the RTS output to go active.
  • Page 239 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description D04:01 Transmitter interrupt condition The interrupt enable bits are used to enable an interrupt when the respective status bit is set in Serial Channel Status A.
  • Page 240 S e r i a l C h a n n e l r e g i s t e r s Transmitter interrupts Mnemonic Description ERXCTS Change in CTS interrupt enable ETXRDY Transmit register empty interrupt enable ETXHALF Transmit FIFO half-empty interrupt enable ERXBC Transmit buffer closed interrupt enable Table 87: Transmitter interrupt enable bits...

  • Page 241: Serial Channel 1, 2 Control Register B

    S e r i a l C o n t r o l l e r M o d u l e Serial Channel 1, 2 Control Register B Address: FFD0 0004 / 44 RDM1 RDM2 RDM3 RDM4 RBGT RCGT Reserved MODE Reserved...
  • Page 242 S e r i a l C h a n n e l r e g i s t e r s Access Mnemonic Reset Description D25:22 Reserved D21:20 MODE SCC mode UART mode Reserved SPI master mode SPI slave mode Configures the serial channel to operate in UART or SPI modes.
  • Page 243 S e r i a l C o n t r o l l e r M o d u l e Access Mnemonic Reset Description D11:09 TENC Transmit encoding D08:06 RDEC Receive data encoding The NS7520 can be programmed to encode and decode the serial data stream using one of the eight methods listed here.
  • Page 244 S e r i a l C h a n n e l r e g i s t e r s Access Mnemonic Reset Description TENC/RDEC continued NRZI-Space (011). A 0 is represented by a transition at the beginning of the bit-time;...

  • Page 245: Serial Channel 1, 2 Status Register A

    S e r i a l C o n t r o l l e r M o d u l e Figure 27 shows the different transmit and receive coding methods. Figure 27: Data coding example Serial Channel 1, 2 Status Register A Address: FFD0 0008 / 48 The receive status bits (D31:16) are stuffed into the StatusOrIndex field in the DMA buffer descriptor when DMA operations are enabled and a buffer is closed.
  • Page 246 S e r i a l C h a n n e l r e g i s t e r s MATCH BGAP CGAP Reserved RXFDB RBRK DCDI ROVER RRDY RHALF RFULL DSRI CTSI TRDY THALF EMPTY Register bit assignment Bits Access Mnemonic...
  • Page 247 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description BGAP Buffer GAP timer Set when the enable receive buffer gap timer is set in Serial Channel Control Register B and the timeout value defined in the Receive Buffer GAP Timer register has expired.
  • Page 248 S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description D21:20 RXFDB Receive FIFO data available Full-word One byte Half-word Three bytes (LENDIAN determines which three) Identifies the number of valid bytes contained in the next long word to be read from the Serial Channel...
  • Page 249 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description RBRK Receive break interrupt pending Indicates that a UART receive break condition has been found.
  • Page 250 S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description RRDY Receive register ready interrupt pending Indicates that data is available to be read from the FIFO Data register.
  • Page 251 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description Receive buffer closed interrupt pending Indicates a receive buffer closed condition. Once set, the RBC bit remains set until acknowledged.
  • Page 252 S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description DSRI Change in DSR interrupt pending Indicates a state change in the EIA data set ready signal.

  • Page 253: Serial Channel 1, 2 Bit-Rate Registers

    S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description Transmit buffer closed interrupt pending Indicates a transmit buffer closed condition. Once set, the TBC bit remains set until acknowledged.
  • Page 254 S e r i a l C h a n n e l r e g i s t e r s CLKM EBIT TDCR Rsvd RDCR MODE Rsvd TICS RSVD RICS Rsvd NREG Register bit assignment Bits Access Mnemonic Reset Description EBIT...
  • Page 255 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description TXSRC Transmit clock source Internal External (input through OUT2 signal) Controls the source of the transmitter clock. The transmitter clock can be provided by an internal source, as determined by the value in the TICS field, or by an input on the OUT2 signal attached to the...
  • Page 256 S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description TXCINV Transmit clock invert Normal; TXD driven on falling edge of TX clock Inverted;...
  • Page 257 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description D20:19 TDCR Transmit divide clock rate 1x clock mode (only NRZ or NRZI allowed) 8x clock mode 16x clock mode 32x clock mode...
  • Page 258 S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description D17:16 RDCR Receive divide clock rate 1x clock mode (only NRZ or NRZI allowed) 8x clock mode 16x clock mode 32x clock mode...
  • Page 259 S e r i a l C o n t r o l l e r M o d u l e Bits Access Mnemonic Reset Description Reserved RICS Receiver internal clock source BRG; the transmitter uses BRG output for its clock DPLL;...
  • Page 260 S e r i a l C h a n n e l r e g i s t e r s FXTALE = xtal/5 = 18.432MHz/5 = 3.6864MHz This does not change with speed grade. Fbrg = FXTALE/[2 * 16 * (N+1)] 115200 = 3686400/2*16*(N+1) 2*16*(N+1) = 3686400/115200 2*16*(N+1) = 32...
  • Page 261 S e r i a l C o n t r o l l e r M o d u l e Max programmable baudrate = 1,440K 16X @ 36.864MHz Fbrg = SYSCLK/[2 * 16 * (N+1)] 1152000 = 36864000/2*16*(N+1) 2*16*(N+1) = 36864000/1152000 2*16*(N+1) = 16 N = 32/32-1 = 0...

  • Page 262: Serial Channel 1, 2 Fifo Registers

    S e r i a l C h a n n e l r e g i s t e r s N register Bit rate CLKMUX X1 mode X8 mode X16 mode 230400 Table 91: Bit rate examples Serial Channel 1, 2 FIFO registers Address: FFD0 0010 / 50 The serial channel FIFO data registers manually interface with the serial controller FIFOs instead of using DMA support.
  • Page 263 S e r i a l C o n t r o l l e r M o d u l e The Receive Buffer Gap Timer register closes out a receive serial data buffer. The timer is reset when the first character is received in a new buffer. New characters are received while the timer operates.

  • Page 264: Serial Channel 1, 2 Receive Character Gap Timer

    S e r i a l C h a n n e l r e g i s t e r s Bits Access Mnemonic Reset Description D14:00 BT timer The required value for the receive buffer gap timer is a function of the channel bit-rate and the maximum receive buffer size.
  • Page 265 S e r i a l C o n t r o l l e r M o d u l e TRUN Reserved Reserved Register bit assignment Bits Access Mnemonic Reset Description TRUN Enable timer to run Set to 1 to allow the receive character gap timer to operate.

  • Page 266: Serial Channel 1,2 Receive Match Register

    S e r i a l C h a n n e l r e g i s t e r s Serial Channel 1,2 Receive Match register Address: FFD0 001C / 5C When the serial channel is configured for UART mode, the Receive Match register provides the data bytes that the receiver uses to compare against the incoming receive data stream.
  • Page 267 S e r i a l C o n t r o l l e r M o d u l e RMMB1 RMMB2 RMMB3 RMMB4 Register bit assignment Bits Access Mnemonic Reset Description D31:24 RMMB1 Receive mask match byte 1 D23:16 RMMB2 Receive mask match byte 2...
  • Page 268 S e r i a l C h a n n e l r e g i s t e r s 2 5 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 269 Electrical Characteristics his chapter provides the electrical specifications and timing relationships integral to NS7520 operation. Electrical specifications include DC and AC characteristics. 2 5 7...

  • Page 270: Dc Characteristics

    D C c h a r a c t e r i s t i c s DC characteristics DC electrical specifications define the power supply voltages and currents, and the I/O voltage and drive characteristics. Recommended operating conditions The NS7520 operates using an internal core V supply voltage of 1.5V.

  • Page 271: Input/Output Characteristics

    E l e c t r i c a l C h a r a c t e r i s t i c s Input/Output characteristics Table 97 shows DC characteristics for inputs. Table 98 shows DC characteristics for outputs.
  • Page 272 D C c h a r a c t e r i s t i c s Figure 28: Internal pullup characteristics Figure 29: Internal pulldown characteristics 2 6 0 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...

  • Page 273: Absolute Maximum Ratings

    E l e c t r i c a l C h a r a c t e r i s t i c s Absolute maximum ratings Table 99 defines the maximum values for the voltages that the NS7520 can withstand without being damaged.
  • Page 274 A C c h a r a c t e r i s t i c s SDRAM SDRAM NS7520 Buffer other memory devices Figure 30: System configuration for specified timing Estimated load Signal (pF) Device loads BCLK Two SDRAMs, 1 clock buffer/clock input to PLD A[27:0], CAS[3:0]_ Two SDRAM An, 1 buffer/PLD...

  • Page 275: Oscillator Characteristics

    E l e c t r i c a l C h a r a c t e r i s t i c s Signal Derating (ns/pF) BCLK 0.069 A[27:0], TS_, TA_, TEA_, BR_, BG_, BUSY_, DATA[31:0] 0.150 BE[3:0] 0.300 CS[4:0]_, CAS[3:0], RW_, WE_, OE_ 0.137...
  • Page 276 O s c i l l a t o r C h a r a c t e r i s t i c s 3R3V SCANEN_ Rise time = 18ns; 0 OHM 0.8V to 2.0V LVC04 RESET_ RESET_ Optional 36.864-55.296MHz Oscillator 3R3V PLL bypassed - U1 &...

  • Page 277: Timing Diagrams

    E l e c t r i c a l C h a r a c t e r i s t i c s Timing Diagrams Timing_Specifications All timing specifications consist of the relationship between a reference clock and a signal: There are bussed and non–bussed signals.

  • Page 278: Reset_Timing

    T i m i n g D i a g r a m s Reset_timing From a cold start, RESET_ must be asserted until all power supplies are above their specified thresholds. An additional 8 microseconds is required for oscillator settling time (allow 40ms for crystal startup).

  • Page 279: Sram Timing

    E l e c t r i c a l C h a r a c t e r i s t i c s SRAM timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load:...
  • Page 280 T i m i n g D i a g r a m s SRAM read CS* controlled read (wait = 2) Note-1 BCLK TA* (Note-4) TEA* (Note-4) TA* (input) A[27:0] Note-2 BE[3:0]* CS[4:0]* read D[31:0] Sync OE* CS0OE* Notes: If the next transfer is DMA, null periods between memory transfers can occur.
  • Page 281 E l e c t r i c a l C h a r a c t e r i s t i c s SRAM burst read CS* controlled, four word (4-2-2-2), burst read (wait = 2, BCYC = 01) Note-1 T1 BCLK TA* (Note-4)
  • Page 282 T i m i n g D i a g r a m s SRAM burst read (2111) CS* controlled read (wait = 0, BCYC = 00) Note-1 BCLK TA* (Note-3) TEA* (Note-3) A[27:0] Note-2 BE[3:0]* CS[4:0]* read D[31:0] Sync OE* CS0OE* Notes: If the next transfer is DMA, null periods between memory transfers can occur.
  • Page 283 E l e c t r i c a l C h a r a c t e r i s t i c s SRAM write CS controlled write (internal and external), (wait = 2) Note-1 BCLK TA* (Note-4) TEA* (Note-4) TA* (input) A[27:0]...
  • Page 284 T i m i n g D i a g r a m s SRAM burst write CS controlled, four word (4-2-2-2), burst write (wait = 2, BCYC = 01) Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) A[27:0] BE[3:0]* (Note-2) CS[4:0]* write D[31:0] Sync WE* CS0WE*...
  • Page 285 E l e c t r i c a l C h a r a c t e r i s t i c s SRAM OE read OE* controlled read (wait = 2) Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) TA* (input) A[27:0] Note-2...
  • Page 286 T i m i n g D i a g r a m s SRAM OE burst read OE* controlled, four word (3-2-2-2), burst read (wait = 2, BCYC = 01) Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) A[27:0] BE[3:0]* (Note-2) CS[4:0]* read D[31:0] Async OE*...
  • Page 287 E l e c t r i c a l C h a r a c t e r i s t i c s SRAM WE write WE* controlled write (wait = 2) Note-1 BCLK TA* (Note-4) TEA*/LAST (note-4) TA* (input) A[27:0] Note-2...
  • Page 288 T i m i n g D i a g r a m s SRAM WE burst write WE* controlled, four word (3-2-2-2), burst write (wait = 2, BCYC = 01) Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) A[27:0] Note-2 BE[3:0]* CS[4:0]* write D[31:0] Async WE*...

  • Page 289: Sdram Timing

    E l e c t r i c a l C h a r a c t e r i s t i c s SDRAM timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load:...
  • Page 290 T i m i n g D i a g r a m s SDRAM read SDRAM read, CAS latency = 2 prechg active read bterm inhibit inhibit BCLK TA* (Note-5) TEA*/LAST* (Note-5) PortA2/AMUX Non-muxed address Muxed address BE[3:0]* (DQM) read D[31:0] CS[4:0]* CAS3* (RAS)
  • Page 291 E l e c t r i c a l C h a r a c t e r i s t i c s SDRAM burst read SDRAM read, CAS latency = 2 prechg active read bterm inhibit inhibit BCLK TA* (Note-5) TEA*/LAST* (Note-5)
  • Page 292 T i m i n g D i a g r a m s SDRAM write SDRAM write prechg active write inhibit BCLK TA* (Note-3) TEA*/LAST* (Note-3) PortA2/AMUX Non-muxed address Muxed address Note-1 BE[3:0]* (DQM) write D[31:0] CS[4:0]* CAS3* (RAS) CAS2* (CAS) CAS1* (WE) CAS0* (A10/AP)
  • Page 293 E l e c t r i c a l C h a r a c t e r i s t i c s SDRAM burst write SDRAM burst write prechg active write write write write inhibit BCLK TA* (Note-3) TEA*/LAST* (Note-3) PortA2/AMUX Non-muxed address...
  • Page 294 T i m i n g D i a g r a m s SDRAM load mode prechg load BCLK CS[4:0]* CAS3* (RAS) CAS2* (CAS) CAS1* (WE) CAS0* (A10/AP) op code A[13:0] SDRAM refresh prechg inhibit refresh BCLK CS[4:0]* CAS3* (RAS) CAS2* (CAS) CAS1* (WE) CAS0* (A10/AP)

  • Page 295: Fp Dram Timing

    E l e c t r i c a l C h a r a c t e r i s t i c s FP DRAM timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max)
  • Page 296 T i m i n g D i a g r a m s FP DRAM read Fast Page read Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) TA* (input) Note-2 BE[3:0]* Non-muxed address Muxed address read D[31:0]1 RAS[4:0]*1 Note-3 CAS[3:0]*1 PortA2/AMUX Notes: If the next transfer is DMA, null periods between memory transfers can occur.
  • Page 297 E l e c t r i c a l C h a r a c t e r i s t i c s FP DRAM burst read Fast Page burst read Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) Note-2 BE[3:0]* Non-muxed address Muxed address...
  • Page 298 T i m i n g D i a g r a m s FP DRAM write Fast Page write Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) TA* (input) Note-2 BE[3:0]* Non-muxed address Muxed address write D[31:0] (FP)RAS[4:0]* Note-3 (FP)CAS[3:0]* PortA2/AMUX Notes: If the next transfer is DMA, null periods between memory transfers can occur.
  • Page 299 E l e c t r i c a l C h a r a c t e r i s t i c s FP DRAM burst write Fast Page burst write Note-1 BCLK TA* (Note-4) TEA*/LAST (Note-4) Note-2 BE[3:0]* Non-muxed address Muxed address...
  • Page 300 T i m i n g D i a g r a m s fp_refresh_cycles Fast page refresh (RCYC = 00) BCLK RAS[4:0]* CAS3* CAS2* CAS1* CAS0* Fast page refresh (RCYC = 01) BCLK RAS[4:0]* CAS3* CAS2* CAS1* CAS0* h (RCYC 2 8 8 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 301 E l e c t r i c a l C h a r a c t e r i s t i c s Fast page refresh (RCYC = 10) BCLK RAS[4:0]* CAS3* CAS2* CAS1* CAS0* Fast page refresh (RCYC = 11) BCLK RAS[4:0]* CAS3*...

  • Page 302: Ethernet Timing

    T i m i n g D i a g r a m s Ethernet timing Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load: 25.0pf Input drive: CMOS buffer Ethernet timing parameters Description Unit TXCLK high to TXD*, TXEN, TXER valid 11.5 RXD*, RXER, RXDV, TXCOL, RXCRS valid to RXCLK high...
  • Page 303 E l e c t r i c a l C h a r a c t e r i s t i c s Ethernet PHY timing TXCLK TXD[3:0],TXEN,TXER RXCLK RXD[3:0],RXER,RXDV,CRS,COL MDIO (input) MDIO (output) Ethernet cam timing RXCLK RPSF_ REJECT_ 2 9 1...

  • Page 304: Jtag Timing

    T i m i n g D i a g r a m s JTAG timing Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load: 25.0pf Input drive: CMOS buffer jtag arm ice timing parameters Description Units TCK to TDO valid...
  • Page 305 E l e c t r i c a l C h a r a c t e r i s t i c s jtag bscan timing parameters Description Units TCK to TDO valid TCK to TDO HighZ TDI setup to TCK rising TDI hold from TCK rising TRST* width TMS setup to TCK rising...

  • Page 306: External Dma Timing

    T i m i n g D i a g r a m s External DMA timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load: 25.0pf Input drive: CMOS buffer External DMA timing parameters Description Unit...
  • Page 307 E l e c t r i c a l C h a r a c t e r i s t i c s Fly-by external DMA BCLK Mem signals (Note-1) DREQ* DACK* DONE* (output) DONE* (input) Note2 Notes: The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*.
  • Page 308 T i m i n g D i a g r a m s Memory-to-memory external DMA Note-1 BCLK Mem signals (Note-2) DREQ* DACK* DONE* (output) Notes: A null period sometimes occurs between memory cycles. The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*.

  • Page 309: Serial Internal/External Timing

    E l e c t r i c a l C h a r a c t e r i s t i c s Serial internal/external timing Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load: 25.0pf Input drive:...
  • Page 310 T i m i n g D i a g r a m s synchronous serial internal clock SCLK Enable synchronous serial external clock SCLK Enable 2 9 8 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...

  • Page 311: Gpio Timing

    E l e c t r i c a l C h a r a c t e r i s t i c s GPIO timing Operating conditions: Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load: 25.0pf Input drive: CMOS buffer...

  • Page 313: Chapter 1 2 : N S 7 5 2 0 E R R A T A

    NS7520 Errata his document contains information about NS7520 errata. 3 0 1...

  • Page 314: How To Identify The Ns7520

    There are three versions of the NS7520, each marked as shown in this sample: 36 MHz version The part number is constructed as follows: [product][package]-[rev id]-[Commercial or Industrial][speed] 36 MHz version: NS7520B-1-C36 46 MHz version: NS7520B-1-I46 55 MHz version: NS7520B-1-C55...

  • Page 315: Ns7520 Errata

    N S 7 5 2 0 E r r a t a NS7520 errata This section lists the known errata for the NS7520, describing each problem and, in most cases, providing a workaround. Clock speed errata using PLL in boundary scan mode Refer to Figure 5 “PLL Mode hardware configuration"...

  • Page 316: Edo Burst Errata

    N S 7 5 2 0 e r r a t a Hardware workaround For each UART, externally clock the CTS signal with the Txd_n signal to guarantee that CTS will not be seen de-asserting at the start of a character. 0 OHM RESET CTS_mod[n]...
  • Page 317 N S 7 5 2 0 E r r a t a Workaround Use the Fast Page setting when using EDO DRAM. 3 0 5 w w w . d i g i e m b e d d e d . c o m...

  • Page 318: Ns7520 Clock Speed Erratum

    N S 7 5 2 0 e r r a t a NS7520 clock speed erratum When the NS7520 is configured to use the PLL clock generator, the system clock can come up at 1/2 the configured frequency, or at a higher frequency — usually 64 MHz. When the PLLTST and BISTEN signals are set high with the SCANEN signal low, the PLL clock generator should produce the system clock based on the code it reads on address signals A[4:0].
  • Page 319 N S 7 5 2 0 E r r a t a 3.3V 3.3V NS7520 SCANEN_N MAX811S RESET_N 74LVC1G04 Monitor with Active output RESET_N Most open drain power monitors require a speedup circuit in order to meet the fall/ rise timing. This next example shows RESET speed up with open drain monitor: Internal 5K Pull-up NS7520 3.3V...

  • Page 320: Spi Slave Mode Errata

    N S 7 5 2 0 e r r a t a SPI slave mode errata SPI slave modes are non-functional. SPI slave logic is unable to sample or drive data on the correct clock edges. This causes byte mismatches. Workaround None.

  • Page 321: Serial Port Error In 7-Bit Mode

    N S 7 5 2 0 E r r a t a Serial port error in 7-bit mode The NS7520’s serial ports do not function correctly when configured in the 7-bit mode. The 7-bit transmitter will transmit 8-bit data, and the data in the receive buffer will be incorrect.

  • Page 322: Station Address Logic: Multicast And Broadcast Packet Filtering

    N S 7 5 2 0 e r r a t a Example 0xffb00010 = 80000001; Wait for the first TIP bit. Reset the TIP bit. Wait for the first TIP bit. Reset the TIP bit. 0xffb00010 = 80ffffff; In this way, the two erroneous timeouts will occur with a small value, and the large value can then be set.

  • Page 323: Corrupt Ethernet Receive Packets

    For those Ethernet packets where the higher level protocol does not provide a checksum, corrupted data might be passed to the application. The problem frequency has been measured at Digi. Tests have shown frequency at one in 20 million for large packets (1518 bytes) and approximately one in 10-500 million for small packets (64 bytes).

  • Page 324: Transmit Buffer Closed Bit Is Not Functional

    N S 7 5 2 0 e r r a t a Transmit buffer closed bit is not functional The transmit buffer closed (TXBC) bit, D01, in Serial Status Register A (Serial Controller module) does not work as described. Workaround To determine when the last character has been transmitted, use the software workaround for the mode you are using: Interrupt mode:...

  • Page 325: External Use Of Ta_ And Tea

    N S 7 5 2 0 E r r a t a Workaround Use the software workaround for the mode you are using: Interrupt mode: For all but the first character, check the TXEMPTY bit (D00 in the Serial Status Register A). If the TXEMPTY bit is not set, write the next character within 1 character –...
  • Page 326 N S 7 5 2 0 e r r a t a 3 1 4 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 327 N S 7 5 2 0 E r r a t a 3 1 5 w w w . d i g i e m b e d d e d . c o m...
  • Page 329 Index BASE field 88 , 93 baudrates with different clock A10/AP support sources A26 bit settings BBus arbitration A27 bit settings BBus master and slave modules abort exception 32 , 35 BBus module 43 - 45 absolute maximum ratings address decoding AC characteristics 261 - 263 Big Endian configuration...
  • Page 330 chip select address range absolute maximum ratings Chip Select Base Address register 88 , 92 input chip select controller outputs pinout recommended operating conditions signal descriptions demand-paged virtual memory system Chip Select Option register DMA buffer descriptor 131 - 133 Chip Select Option Register A DMA channel assignments Chip Select Option Register B...
  • Page 331 receive buffer descriptor selection EDO DRAM receive FIFO burst cycles receive processing EDO DRAM controller 109 - 111 transmit FIFO EFE receive processing transmit processing EFE transmit processing Ethernet General Control register electrical characteristics 257 - 299 Ethernet General Status register electrical specifications, AC external CAM filtering ENDEC...
  • Page 332 Ethernet receive and transmit FIFO management interrupts receive FIFO interface Ethernet Receive Status register Ethernet receiver considerations transmit FIFO interface Ethernet timing 290 - 291 FIFO overrun condition Ethernet Transmit Status register FIRQ Ethernet transmitter considerations FIRQ exception 32 , 36 exception entry/exit summary FIRQ lines exceptions...
  • Page 333 general-purpose I/O Interrupt Enable register pinout Interrupt Enable Set register signal descriptions interrupt pending bits glueless connection interrupt request exception. exception. glueless interface interrupt service routine (ISR) GPIO configuration interrupt sources 40 - 41 GPIO pins 2 , 3 DMA interrupts GPIO timing Ethernet receive and transmit interrupts...
  • Page 334 memory-to-memory operation MII Management Address register MAC Configuration register 1 MII Management Command register MAC Configuration register 2 MII Management Configuration MAC module 154 - 155 register MASK field 88 , 97 MII Management Indicators register Maximum Frame register MII Management Read Data register media access controller.
  • Page 335 PORTC interrupts power operating frequency 4 , 6 power supply operating voltage prefetch abort exception 32 , 35 oscillator characteristics processor interrupts vs. DMA output drive programmable timers 2 , 4 outputs, DC characteristics read-to-write operations pad operation receive buffer descriptor selector pad pulldown characteristics receive buffer size selection pad pullup characteristics...
  • Page 336 SDRAM timing 277 - 282 register Serial Channel 1,2 Bit-Rate registers Serial Channel 1,2 Status Register Serial Channel 1,2 Control Register A serial port performance receiver interrupts SPI mode 211 - 220 transmitter interrupts FIFO management Serial Channel 1,2 Control Register B master mode 214 - 217 Serial Channel 1,2 FIFO registers...
  • Page 337 SRAM timing 267 - 276 Timer Control registers static memory controller. SRAM Timer Status register controller. timing diagrams 265 - 299 Station Address Filter register timing specifications station address logic. SAL. transmit FIFO Station Address registers secondary address StatusOrIndex field 169 , 173 transmit FIFO interface swap instruction...
  • Page 338 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7...
  • Page 339 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Digi International NS7520B-1-C55 NS7520B-1-I55...

This manual is also suitable for:

Ns7520b seriesNs7520b-1-i46Ns7520b-1-c55

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