Reset_Timing - Digi NS7520B-1-C36 Hardware Reference Manual

T i m i n g D i a g r a m s

Reset_timing

From a cold start, RESET_ must be asserted until all power supplies are above their
specified thresholds. An additional 8 microseconds is required for oscillator settling
time (allow 40ms for crystal startup).
Due to an internal three flip-flop delay on the external RESET_ signal, after the
oscillator is settled, RESET_ must be asserted for three periods of the XTALA1 clock in
these situations:
Before release of reset after application of power
While valid power is maintained to initiate hot reset (reset while power is
at or above specified thresholds)
Before loss of valid power during power outage/power down
The PORTC4 output indicates the reset state of the chip. PORTC4 persists beyond the
negation of RESET_ for approximately 512 system clock cycles if the PLL is disabled.
When the PLL is enabled, PORTC4 persists beyond the negation of RESET_ to allow for
PLL lock for 100 microseconds times the ratio of the VCO to XTALA.
VDD, VCC
XTALA1
RESET_
Reset timing parameters
Num
1
2
3
4
Note: RESET_ should remain low for at least 40ms after power reaches 3.0V.
2 6 6
1
2
Description
Power valid before reset negated
Reset asserted after power valid
Reset asserted while power valid
Reset asserted before power invalid
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
3 3
Min Typ Max
40
3
3
3
4
Units
ms
See note
following table.
T
XTALA1
T
XTALA1
T
XTALA1