Digi NS7520B-1-C36 Hardware Reference Manual page 174

E F E c o n f i g u r a t i o n
Bits
D09
D08
D07:02
D01:00
Table 53: Ethernet General Control register bit definition
ENDEC mode and NS7520 pins
Table 54 shows the relationship between the lower bits in the Ethernet General
Control register and the NS7520 pins that they control. The NS7520 pins are
controlled by these bits only when the MODE field (D15:14) is set to ENDEC.
1 6 2
Access Mnemonic Reset
R/W MAC_RESET 0
R/W ITXA 0
R/W PDN: 0
AUI_TP:
LNK_DIS:
LPBK:
UTP_STP
R/W EXINT 0
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Description
MAC software reset
0 Restore MAC to normal operation
1 Reset MAC host interface
Insert transmit source address
When set, forces the MAC to automatically insert the
Ethernet source MAC address into the Ethernet transmit
packet. The MAC address information is provided by the
data configured in the Station Address registers (SA1, SA2,
SA3).
th
When ITXA is cleared, the 7
Ethernet packet are ignored and replaced by the size bytes
in the MAC Address register.
ENDEC media control bits
Used only when the MODE field is configured for ENDEC
mode. In this configuration, each register bit is mapped to
NS7520 pins, allowing the software to manipulate control
signals on an external ENDEC PHY device.
See Table 54 on page 163 for more information.
External interface mode
00 MII normal operation, used for all MII-style 10/100
PHY devices
01 TP-PMD mode, used for PHYs that contain their
own non-standard PCS circuitry
10 10 Mbit mode, used for older
10-Mbit-only PHY devices that predate the MII
standard.
11 Reserved
th
through 12 bytes in the