Digi NS7520B-1-C36 Hardware Reference Manual page 242

S e r i a l C h a n n e l r e g i s t e r s
Bit
D25:22
D21:20
D19
D18:16
D15
D14:12
Table 88: Serial Channel Control Register B bit definition
2 3 0
Access Mnemonic
N/A Reserved
R/W MODE
R/W BITORDR
N/A Reserved
R/W RTSTX
N/A Reserved
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Reset Description
N/A N/A
0 SCC mode
00 UART mode
01 Reserved
10 SPI master mode
11 SPI slave mode
Configures the serial channel to operate in UART or
SPI modes. The MODE field must be established
before the CE bit in Serial Channel Control Register
A is set to 1.
0 Bit ordering
0 Normal; transmit/receive LSB (least significant
bit) first
1 Reverse; transmit/receive MSB (most significant
bit) first
Controls the order in which bits are transmitted and
received in the Serial Shift register.
When BITORDR is set to 0, the bits are
processed LSB first, MSB last.
When BITORDR is set to 1, the bits are
processed MSB first, LSB last.
N/A N/A
0 Enable active RTS only while transmitting
Note: The RTS bit in Serial Channel Control
Register A must be set if setting this bit.
Controls the RTS indicator. Do not set this bit if the
RTSRX bit in Serial Channel Control Register A is
set.
When this bit is set, the RTS output goes active only
when the transmitter is actively sending a transmit
character. The RTSTX bit allows external hardware to
use the RTS signal as a transmit line driver enable
signal in
multi-drop applications.
N/A N/A