Transmit And Receive Fifos; Efe Transmit Processing; Efe Receive Processing - Digi NS7520B-1-C36 Hardware Reference Manual

EFE logic provides all control and status registers required by the Ethernet module.
The transmitter and receiver each provide a 16-bit status word after processing each
Ethernet frame. These status words can be given to the CPU on an interrupt basis or
moved automatically to the DMA buffer descriptor for the associated Ethernet frame.

Transmit and receive FIFOs

The EFE contains a 512-byte transmit FIFO and a 2048-byte local receive FIFO (storing
filtered packets):
Transmit FIFO. Allows the critical portion of the transmit buffer to wait in
the FIFO while collisions occur on the Ethernet medium. This scheme
removes the need for the transmitter to fetch the buffer multiple times
from memory.
Receive FIFO. Allows the entire Ethernet frame to be received and wait in
the FIFO while the receive byte count is analyzed. The receive byte count is
analyzed to determine the optimum buffer descriptor for DMA transfer. The
DMA channel assigned to the Ethernet receiver can use one of four
differently sized receive buffers. Only successfully received frames, with
acceptable destination addresses, are committed to external system
memory.

EFE transmit processing

The NS7520 Ethernet transmit DMA channel addresses one list of buffer descriptors
per packet to be transmitted. The Ethernet transmit DMA channel moves Ethernet
packets corresponding to this buffer descriptor list to the local FIFO in the EFE
module.

EFE receive processing

The MAC block receives good Ethernet packets (those with a valid checksum and
size); bad packets (those with invalid checksum, fragment errors, bad size, etc.) are
discarded automatically.
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