Digi NS7520B-1-C36 Hardware Reference Manual page 297

FP DRAM burst read
Fast Page burst read
T1
BCLK
TA* (Note-4)
TEA*/LAST (Note-4)
36
Note-2
BE[3:0]*
6
Non-muxed address
35
Muxed address
read D[31:0]
28
OE*
27
RAS[4:0]*
Note-3
CAS[3:0]*
PortA2/AMUX
12
RW*
Notes:
If the next transfer is DMA, null periods between memory transfers can occur.
1
Thirteen clock pulses are required for DMA context switching.
Port size determines which byte enable signals are active:
2
8-bit port = BE3*
–
16-bit port = BE[3:2]
–
– 32-bit port = BE[3:0]
Port size determines which CAS signals are active:
3
8-bit port = CAS3*
–
16-bit port = CAS[3:2]
–
32-bit port = CAS[3:0]
–
The TA* and TEA*/LAST signals are for reference only.
4
TW T2 TW T2
30 30
11
10
43 43
37
w w w . d i g i e m b e d d e d . c o m
E l e c t r i c a l C h a r a c t e r i s t i c s
TW T2 TW T2
31
27
Note-1 T1
31
36
28
37
2 8 5