Ns7520 Dram Address Multiplexing; Using The Internal Multiplexer - Digi NS7520B-1-C36 Hardware Reference Manual

BCLK
CS_
ADDR[31:4]
ADDR[3:1]
R/W_
WE_
OE_
BE0_
BE1_
DATA
TA_
Figure 8: SRAM synchronous burst read cycle

NS7520 DRAM address multiplexing

The NS7520 can be configured to use an internal DRAM address multiplexer or an
external address multiplexer. A combination of the AMUX and AMUX2 bits in the
MMCR and the DMUXS bit in the Chip Select Base Address register determines which
multiplexer is used.

Using the internal multiplexer

When configured to use the internal address multiplexer, the DRAM address signals
are provided on system bus address pins A13:A0.
A 32-bit DRAM peripheral connects to A13 through A2.
A 16-bit DRAM peripheral connects to A13 through A1.
An 8-bit DRAM peripheral connects to A13 through A0.
T1 T2 T2 T2
000 001 010
M e m o r y C o n t r o l l e r M o d u l e
T2 T2 T2 T2
011 100 101 110
w w w . d i g i e m b e d d e d . c o m
T2
111
1 0 5