Digi NS7520B-1-C36 Hardware Reference Manual page 285

SRAM OE read
OE* controlled read (wait = 2)
BCLK
TA* (Note-4)
TEA*/LAST (Note-4)
TA* (input)
A[27:0]
Note-2
BE[3:0]*
CS[4:0]*
read D[31:0]
Async OE*
CS0OE*
RW*
Notes:
At least one null period occurs between memory transfers. More null periods can
1
occur if the next transfer is DMA. Thirteen clock pulses are required for DMA
context switching.
Port size determines which byte enable signals are active:
2
8-bit port = BE3*
–
– 16-bit port = BE[3:0]
32-bit port = BE[3:0]
–
The TW cycles are present when the WAIT field is set to 2 or more.
3
The TA* and TEA*/LAST signals are for reference only.
4
T1 TW
30
31
6
36
27
28
18
12
w w w . d i g i e m b e d d e d . c o m
E l e c t r i c a l C h a r a c t e r i s t i c s
T2 Note-1
30
31
15
14
36
27
11
10
28
18
T1
2 7 3