Mii Management Configuration Register - Digi NS7520B-1-C36 Hardware Reference Manual

MII Management Configuration register

Address: FF80 0420
31 30
15 14
RMIIM
Register bit assignment
Bits
D31:16
D15
D14:05
D04:02
D01
D00
Table 69: MII Management Configuration register bit definition
29 28 27 26
13 12 11 10
Reserved
Access Mnemonic Reset
N/A Reserved N/A
R/W RMIIM 0
N/A Reserved N/A
R/W CLKS N/A
R/W SPRE 0
R/W SCANI 0
25 24 23 22 21
Reserved
9 8 7 6 5
Description
N/A
Reset MII management
Set this bit to 1 to reset the MII management module.
N/A
Clock select
Used by the clock divide logic when creating the MII
management clock (MDC pin). The IEEE 802.3u standard
requires that the clock be no faster than 2.5 MHz. See
Table 70: "CLKS field settings" on page 190 for examples.
Note: Some PHY devices support clock rates up to
12.5 MHz.
Suppress preamble
1 The MII management module performs read/write
cycles without the 32-bit preamble field.
0 Normal cycles are performed.
Note: Some PHY devices support suppressed
preamble.
Scan increment (single scan for read data)
When set to 1, the MII management module performs read
cycles across a range of PHY devices, from address 1
through the value set in the RADR field in the MII Address
register (see page 192).
w w w . d i g i e m b e d d e d . c o m
E t h e r n e t M o d u l e
20 19 18 17 16
4 3 2 1 0
CLKS SPRE SCANI
1 8 9