Non-Back-To-Back Inter-Packet-Gap Register - Digi NS7520B-1-C36 Hardware Reference Manual

Non-Back-to-Back Inter-Packet-Gap register

Address: FF80 040C
31 30
15 14
Rsvd
Register bit assignment
Bits
D31:15
D14:08
D07
D06:00
Table 64: Non-Back-to-Back Inter-Packet-Gap register bit definition
29 28 27 26
13 12 11 10
IPGR1
Access Mnemonic Reset
N/A Reserved N/A
R/W IPGR1 N/A
N/A Reserved N/A
R/W IPGR2 N/A
25 24 23 22 21
Reserved
9 8 7 6 5
Rsvd
Description
N/A
Non back-to-back inter-packet-gap — part 1
A programmable field that represents the optional
carrierSense window (referenced in IEEE 802.3 "Carrier
Deference").
If carrier is found during IPGR1 timing, the MAC defers to
the carrier. If carrier is found after IPGR1 times out, the
MAC continues timing IPGR2. The transmitter causes a
collision, activating the random back off fairness algorithm
(ensuring fair access to the medium).
The range of values for IPGR1 is
The default value is
'hC (12d)
N/A
Non-back-to-back inter-packet-gap—part 2
A programmable field that represents the non-back-to-back
inter-packet-gap.
The default setting for IPGR2 is
represents these minimum IPG values:
In 100 Mbps: 0.96 μs
In 10 Mbps: 9.6 μs
w w w . d i g i e m b e d d e d . c o m
E t h e r n e t M o d u l e
20 19 18 17 16
4 3 2 1 0
IPGR2
.
'h0—IPGR2
.
, which
'h12 (18d)
1 8 3