Digi NS7520B-1-C36 Hardware Reference Manual page 35

GPIO Serial
signal signal
2
PORTC1 CTSB_
2
PORTC0 TXCB/
OUT2B_/
DCDB_
Table 9: GPIO pinout
Notes:
RESET output indicates the reset state of the NS7520. PORTC4 persists beyond
1
the negation of RESET_ for approximately 512 clock cycles if the PLL is disabled.
When the PLL is enabled, PORTC4 persists beyond the negation of RESET_ to
allow for PLL lock for 100 microseconds times the ratio of the VCO to XTALA.
Note that this GPIO is left in output mode active following a hardware
RESET.
*PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to
2
be synchronous to any clock. The interrupt remains active until cleared by a
change in the input signal level.
Signal descriptions
See Chapter 6, "GEN Module," for signal and configuration information for PORTA and
PORTC.
Other
signal Pin I/O
LIRQ1/ E12 U I/O
DONE2_
(O)
LIRQ0/ E14 U I/O
DONE2_(I)
w w w . d i g i e m b e d d e d . c o m
P i n o u t a n d P a c k a g i n g
Serial channel Other
OD description description
2 Channel 2 CTS_ Level sensitive
IRQ/DMA
channel 4/6
DONE_out
2 Pgm'able Out/ Level sensitive
Channel 2 DCD/ IRQ/DMA
Channel 2 SPI channel 4/6
enable (SEL_)/ DONE_in
Channel 2
TXCLK
2 3