Sdram Read Cycles - Digi NS7520B-1-C36 Hardware Reference Manual

S D R A M

SDRAM read cycles

Figure 11 and Figure 12 provide timing examples for SDRAM normal and burst reads,
respectively, with WAIT and BCYC configured with a value of 0.
CAS3_(RAS_)
CAS2_(CAS_)
CAS1_(WE_)
TA_ {output}
TEA_(LAST_) {output}
TEA_(LAST_) {input}
Figure 11: SDRAM normal read
1 2 0
BCLK
TS_
RW_
BE[3:0]
D[31:0]
CS[7:0]_
A[13:0]
AMUX
TA_ {input}
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
precharge activate
One Valid Per Cycle
read bstop