Digi NS7520B-1-C36 Hardware Reference Manual page 239

Bits Access Mnemonic
D04:01 R/W IE
D00 R/W ETXDMA
Table 85: Serial Channel Control Register A
Receiver interrupts
Bit Mnemonic
D15 ERXBRT
D14 ERFE
D13 ERXPE
D12 ERXORUN
D11 ERXRDY
D10 ERXHALF
D09 ERXBC
D07 ERXDCD
D06 ERXRI
D05 ERXDSR
Table 86: Receiver interrupt enable bits
Reset Description
0 Transmitter interrupt condition
The interrupt enable bits are used to enable an
interrupt when the respective status bit is set in Serial
Channel Status A.
Setting the IE field to 1 enables the interrupt.
Setting the IE field to 0 disables the interrupt.
Table 87, "Transmitter interrupt enable bits," on
page 228, lists individual bit numbers and
descriptions.
0 Enable transmit DMA requests
Enables the transmitter to interact with a DMA
channel. When configured to operate in DMA mode,
the DMA controller loads the transmit data FIFO from
memory.
Clear this bit to pause the transmitter.
Description
Receive break interrupt enable
Receive framing error interrupt enable
Receive parity error interrupt enable
Receive overrun interrupt enable
Receive register ready interrupt enable
Receive FIFO half-full interrupt enable
Receive buffer closed interrupt enable
Change in DCD interrupt enable
Change in RI interrupt enable
Change in DSR interrupt enable
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