Timing Diagrams
Timing_Specifications
All timing specifications consist of the relationship between a reference clock and a
signal:
There are bussed and non–bussed signals. Non–bussed signals separately
illustrate 0–to–1 and 1–to–0 transitions.
Inputs have setup/hold times versus clock rising.
Outputs have switching time relative to either clock rising or clock falling.
Note:
Clock
Signal
Bus
Timing relationships in this diagram are drawn without proportion to actual
delay.
0-to-1 from rising edge
0-to-1 from falling edge
Setup time
Hold time
Valid from falling edge
Setup time
E l e c t r i c a l C h a r a c t e r i s t i c s
1-to-0 from rising edge
1-to-0 from falling edge
Valid from rising edge
Hold
w w w . d i g i e m b e d d e d . c o m
2 6 5
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