Digi NS7520B-1-C36 Hardware Reference Manual page 274

A C c h a r a c t e r i s t i c s
NS7520
Figure 30: System configuration for specified timing
Signal
BCLK
A[27:0], CAS[3:0]_
CS[4:0]_
DATA[31:0]
BE*_
TS_, TA_, TEA_, BR_, BG_, BUSY_, WE_,
OE_
PORTA3, PORTA1, PORTC3, PORTC1
(operating external DMA)
Other PORTA[*] and PORTC[*], TDO
MDC, MDIO, TXEN, TXER, TXD[3:0]
Table 100: System loading details
Exceeding the loading shown in Table 100 can result in additional signal delay. The
delay can be approximated by derating the output buffer based on the expected load
capacitance per the values shown in Table 101.
2 6 2
SDRAM
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
SDRAM
Buffer
other
memory
devices
Estimated load
(pF) Device loads
23 Two SDRAMs, 1 clock buffer/clock
input to PLD
23 Two SDRAM An, 1 buffer/PLD
13 Two SDRAM CSn, 1 buffer PLD
18 One SDRAM DQ, 1 buffer/PLD
19 One SDRAM DQ, 1 buffer/PLD
15 1 buffer/PLD
15 1 buffer/PLD
85 Tester load
20 One PHY