Back-To-Back Inter-Packet-Gap Register - Digi NS7520B-1-C36 Hardware Reference Manual

E F E c o n f i g u r a t i o n

Back-to-Back Inter-Packet-Gap register

Address: FF80 0408
31 30
15 14
Register bit assignment
Bits
D31:07
D06:00
Table 63: Back-to-Back Inter-Packet-Gap register bit definition
1 8 2
29 28 27 26
13 12 11 10
Reserved
Access Mnemonic Reset
N/A Reserved N/A
R/W IPGT N/A
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
25 24 23 22 21
Reserved
9 8 7 6 5
Description
N/A
Back-to-back inter-packet-gap
A programmable field that represents the nibble time offset
of the minimum possible period between the end of any
transmitted packet to the beginning of the next packet.
Full-duplex mode. The register value should be the
proper period in nibble times minus 3.
The recommended setting is
represents these minimum IPG values:
— In 100 Mbps: 0.96 μs
— In 10 Mbps: 9.6 μs
Half-duplex mode. The register value should be the
proper period in nibble times minus 6.
The recommended setting is
represents these minimum IPG values:
— In 100 Mbps: 0.96 μs
— In 10 Mbps: 9.6 μs
20 19 18 17 16
4 3 2 1 0
IPGT
, which
'h15 (21d)
, which
'h12 (18d)