Digi NS7520B-1-C36 Hardware Reference Manual page 94

I n t e r r u p t s
Bits
D31:19
D18
D17
D16
D15
D14
D13
D12
D11:08
D07
D06
D05
D04
D03
D02
D01
D00
Table 33: Interrupt Enable registers bit definition
8 2
Access Mnemonic Reset
R/W DMA1–13 0
N/A Reserved N/A
R/W ENET1RX 0
R/W ENET1TX 0
R/W SER 1 RX 0
R/W SER 1 TX 0
R/W SER 2 RX 0
R/W SER 2 TX 0
N/A Reserved N/A
R/W MAC1 0
R/W 0
WATCHDOG
R/W TIMER 1 0
R/W TIMER 2 0
R/W PORTC3 0
R/W PORTC2 0
R/W PORTC1 0
R/W PORTC0 0
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Description
The DMA1 through DMA13 bit positions correspond to
interrupts sourced by DMA channel 1 through 13.
N/A
The ENET1RX bit position corresponds to an interrupt
sourced by the Ethernet receiver.
The ENET1TX bit position corresponds to an interrupt
sourced by the Ethernet transmitter.
The SER 1 RX bit position corresponds to an interrupt
sourced by the Serial Channel A receiver.
The SER 1 TX bit position corresponds to an interrupt
sourced by the Serial Channel A transmitter.
The SER 2 RX bit position corresponds to an interrupt
sourced by the Serial Channel B receiver.
The SER 2 TX bit position corresponds to an interrupt
sourced by the Serial Channel B transmitter.
N/A
The MAC1 bit position corresponds to an interrupt sourced
by the Ethernet MAC 1.
The WATCHDOG bit position corresponds to an interrupt
condition sourced by the watchdog timer.
The TIMER 1 bit position corresponds to an interrupt
condition sourced by the TIMER 1 module.
The TIMER 2 bit position corresponds to an interrupt
condition sourced by the TIMER 2 module.
The PORTC3 bit position corresponds to an interrupt
condition sourced by the PORTC3 input.
The PORTC2 bit position corresponds to an interrupt
condition sourced by the PORTC2 input.
The PORTC1 bit position corresponds to an interrupt
condition sourced by the PORTC1 input.
The PORTC0 bit position corresponds to an interrupt
condition sourced by the PORTC0 input.