Fp Dram Timing - Digi NS7520B-1-C36 Hardware Reference Manual

FP DRAM timing

BCLK max frequency: 55.296 MHz
Operating conditions:
Temperature:
Voltage:
Output load:
Input drive:
FP DRAM timing parameters
Num
36
6
9
13
10
11
14
15
28
29
30
31
37
35
43
27
12
-15.00 (min) 110.00 (max)
1.60 (min) 1.40 (max)
25.0pf
CMOS buffer
Description
BCLK high to BE* valid
BCLK high to address valid
BCLK high to data out valid
BCLK high to data out high impedance
Data in valid to BCLK high (setup)
BCLK high to data in invalid (hold)
TA* valid to BCLK high (setup)
BCLK high to TA* invalid (hold)
BCLK low to OE* valid
BCLK low to WE* valid
BCLK high to TA* valid
BCLK high to TEA* valid
BCLK high to PORTA2/AMUX valid
BCLK high to muxed address valid
BCLK low to CAS* valid
BCLK low to RAS* valid
BCLK high to RW* valid
E l e c t r i c a l C h a r a c t e r i s t i c s
Min Max
15.5
5 13.5
14
13
5
3
5
3
12.5
13
13.5
16
14
6 14.5
13
12
13.5
w w w . d i g i e m b e d d e d . c o m
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 8 3