Digi NS7520B-1-C36 Hardware Reference Manual page 259

Bits Access Mnemonic
D13 N/A Reserved
D12 R/W RICS
D11 N/A Reserved
D10:00 R/W NREG
Table 90: Serial Channel Bit-Rate register bit definition
Max baudrates with different clock sources
Max baud rates for the serial port depend on the clock source you are using.
With the 18.432MHz crystal using XTALE as the clock source:
Reset Description
N/A N/A
0 Receiver internal clock source
0 BRG; the transmitter uses BRG output for its
clock
1 DPLL; the receiver uses the extracted clock
provided by the DPLL.
When the RXSRC field is set to 0, the receiver
operates using an internal clock. There are two
sources for internal clocks: the bit-rate generator
(BRG) and the receiver digital phase lock loop
(DPLL). The BRG uses a divider mechanism for
clock generation. The DPLL extracts the clock from
the incoming receive data stream.
N/A N/A
0 N register
The N register value is determined by the following
equations. F must be adjusted according to the
BRG
TMODE and TDCR/RDCR settings. For a 16x
setting, for example, F
baud rate.
F = F /[2*(N+1)
BRG XTALE
Using a CLKMUX setting of 00
F = F /[2*(N+1)
BRG SYSCLK
Using a CLKMUX setting of 01
F = F /[2*(N+1)
BRG OUT1
Using a CLKMUX setting of 10
F = F /[2*(N+1)
BRG OUT2
Using a CLKMUX setting of 11
The maximum value for F
F /4.
SYSCLK
See Table 91: "Bit rate examples" on page 249 for
sample bit rates.
w w w . d i g i e m b e d d e d . c o m
S e r i a l C o n t r o l l e r M o d u l e
is 16 times the desired
BRG
and F is
OUT1 OUT2
2 4 7