Digi NS7520B-1-C36 Hardware Reference Manual page 230

S P I m o d e
occur, regardless of the SPI clock signal. The SPI enable function allows for multiple
slaves to be addressed individually during a multi-drop configuration.
Signals
The GEN module must be configured appropriately to allow the SPI interface signals
to interface with the PORTA and PORTC GPIO pins (see "PORTA Configuration register"
on page 73 and "PORTC Configuration register" on page 77).
Configuration
The SER module must be configured properly to operate in either master or slave
mode. For slave mode operation, the MODE field in Serial Channel Control Register B
must be set to 11 before the CE field in Serial Channel Control Register A is set to 1.
Use this suggested configuration order for SPI slave mode:
Reset the serial port by writing a 0 to Serial Channel Control Register a.
1
Configure the Serial Channel Bit-Rate register, as shown:
2
–
–
–
–
–
–
–
–
–
–
Configure the buffer GAP timer, if you want. The buffer GAP timer terminates a
3
DMA transfer at a programmable interval from the time the first character is
received. (See "Serial Channel 1, 2 Receive Buffer Gap Timer," beginning on page
250, for more information).
Configure the character GAP timer, if you want. The character GAP timer
4
terminates a DMA transfer if the time between the receipt of two characters
exceeds a programmable interval. (See "Serial Channel 1, 2 Receive Character
Gap Timer," beginning on page 252, for more information.)
Configure Serial Channel Control Register B, as shown:
5
–
2 1 8
EBIT: 1 for enable
TMODE: 1 for 1x mode
RXSRC: 1 for external;
TXSRC: 1 for external;
RXEXT: 0 for disable
TXEXT: 0 for disable
CLKMUX: n/a (external timing source)
TXCINV: 0 for normal
RXCINV: 0 for normal
N: n/a (external timing source)
RBGT: 1 to enable the buffer GAP timer
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7