Mii Management Address Register - Digi NS7520B-1-C36 Hardware Reference Manual

E F E c o n f i g u r a t i o n

MII Management Address register

Address: FF80 0428
31 30
15 14
Reserved
Register bit assignment
Bits
D31:13
D12:08
D07:05
D04:00
Table 72: MII Management Address register bit definition
1 9 2
29 28 27 26
13 12 11 10
DADR
Access Mnemonic Reset
N/A Reserved N/A
R/W DADR 0
N/A Reserved N/A
R/W RADR 0
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
25 24 23 22 21
Reserved
9 8 7 6 5
Reserved
Description
N/A
MII PHY device address
Represents the 5-bit PHY device address field for
management cycles. Up to 31 different PHY devices can be
addressed; address 0 is reserved.
N/A
MII PHY register address
Represents the 5-bit PHY register address field for
management cycles. Up to 32 registers within a single PHY
device can be addressed.
20 19 18 17 16
4 3 2 1 0
RADR