Digi NS7520B-1-C36 Hardware Reference Manual page 79

Bits Access Mnemonic
D05:04 R/W BSYNC
D03:00 N/A Reserved
Table 24: System Control register bit definition
Reset Description
0 TA_ input synchronizer
Defines the level of synchronization performed within the
NS7520 for TA_ input:
00 1-stage synchronizer
01 1-stage synchronizer
10 2-stage synchronizer
11 Do not use this setting
The NS7520 can process the TA_ input signal using a 1-
stage flip-flop synchronizer or a 2-stage synchronizer. A
1- or 2-stage synchronizer must be used when TA_ input
is asynchronous to the BCLK signal.
Note: The 2-stage synchronizer is preferable, as it
introduces one additional BCLK of latency in
the access cycle.
N/A N/A
w w w . d i g i e m b e d d e d . c o m
G E N M o d u l e
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