Digi NS7520B-1-C36 Hardware Reference Manual page 250

S e r i a l C h a n n e l r e g i s t e r s
Bits
D11
D10
Table 89: Serial Channel Status Register A bit definition
2 3 8
Access Mnemonic
R RRDY
R RHALF
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Reset Description
0 Receive register ready interrupt pending
Indicates that data is available to be read from the
FIFO Data register. Before reading the FIFO Data
register, the RXFDB field in this register must be read
to determine how many active bytes are available
during the next read of the FIFO Data register. RRDY
typically is used only in interrupt-driven applications;
it is not used for DMA operation. The RRDY status
condition can be programmed to generate an interrupt
by setting the related IE bit in Serial Channel Control
Register A.
RRDY is never active while RBC is active. The RBC
bit must be acknowledged to activate RRDY. When
the receiver is configured to operate in DMA mode,
the interlock between RBC and RRDY is handled
automatically in hardware.
0 Receive FIFO half-full interrupt pending
Indicates that the receive data FIFO contains at least
16 bytes. RHALF typically is used only in interrupt-
driven applications; it is not used for DMA operation.
The RHALF status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.