Transmit Buffer Closed Bit Is Not Functional; Transmit Fifo Timing Issue - Digi NS7520B-1-C36 Hardware Reference Manual

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Transmit buffer closed bit is not functional

The transmit buffer closed (TXBC) bit, D01, in Serial Status Register A (Serial
Controller module) does not work as described.
Workaround
To determine when the last character has been transmitted, use the software
workaround for the mode you are using:
Interrupt mode:
There are three options in interrupt mode:
Waiting
1
–
–
Polling TXEMPTY
2
Poll TXEMPTY (bit 0) in Serial Channel Status Register A. When the bit
indicates empty, allow 1 character time to let the last character exit the
shift register.
Using TXHALF interrupt
3
You can use this method when filling the FIFO using word writes (32-bit
transfers).
Enable the TXHALF interrupt by setting bit 2 in Serial Channel Control
Register A. When this interrupt occurs, it indicates that there are no more
than 16 bytes remaining in the FIFO. Once it occurs, wait 17 character
times — 16 plus 1 character time to allow the last character to exit the shift
register.
DMA mode:
Wait 33 character times after receiving the DMA complete interrupt.

Transmit FIFO timing issue

When transmitting characters from the FIFO, you must be sure each character is
shifted out before the next character is processed. Otherwise, the first clock and
data bit of the new character can be corrupted.
3 1 2
If the FIFO was filled using byte writes, wait 9 character times.
If the FIFO was filled using word writes, wait 33 character times.
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