Digi NS7520B-1-C36 Hardware Reference Manual page 152

D M A c h a n n e l r e g i s t e r s
Bits
REQ continued
D22
D21
D20
D19:18
Table 50: DMA Control register bit definition
1 4 0
Access Mnemonic Reset
N/A Reserved N/A
R/W SINC_ 0
R/W DINC_ 0
N/A Reserved N/A
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Description
DMA channels 4/6 interface with an external peripheral
using handshaking signals multiplexed through PORTC.
When REQ is set to 0 in DMA channel 4 and set to 1
in DMA channel 6, DMA channel 6 is tied to the
external DMA port through PORTC.
When REQ is set to 1 in DMA channel 4, that channel
is tied to the external DMA port through PORTC, no
matter the REQ bit setting in DMA channel 6.
These bits should not be set in any channels other than
DMA 3, 4, 5, or 6.
N/A
Source address increment
0 Increment source address pointer
1 Do not increment source address pointer
Controls whether the source address pointer is incremented
after each DMA transfer. The DMA controller uses this bit
in all modes when referring to a memory address. This bit
is ignored when the source is a fly-by port.
Destination address increment
0 Increment destination address pointer
1 Do not increment destination address pointer
Controls whether the destination address pointer is
incremented after each DMA transfer. The DMA controller
uses this bit in all modes when referring to a memory
address. This bit is ignored when the destination is a fly-by
port.
For memory-to-memory operation with
is written to the specified destination address and all
subsequent data are written are written to the specified
destination address+4.
N/A
, the data
DINC_=0