Digi NS7520B-1-C36 Hardware Reference Manual page 146

D M A c h a n n e l r e g i s t e r s
The DMA Control register should be written to enable the DMA channel only after all
other registers and descriptors are valid.
Address
FF90 0000
FF90 0010
FF90 0014
FF90 0020
FF90 0030
FF90 0034
FF90 0040
FF90 0050
FF90 0054
FF90 0060
FF90 0070
FF90 0074
FF90 0080
FF90 0090
FF90 0094
FF90 00A0
FF90 00B0
FF90 00B4
FF90 00C0
FF90 00D0
FF90 00D4
FF90 00E0
FF90 00F0
FF90 00F4
FF90 0100
FF90 0110
1 3 4
Description
DMA 1 "A" Buffer Descriptor Pointer register
DMA 1 "A" Control register
DMA 1 "A" Status register
DMA 1 "B" Buffer Descriptor Pointer register
DMA 1 "B" Control register
DMA 1 "B" Status register
DMA 1 "C" Buffer Descriptor Pointer register
DMA 1 "C" Control register
DMA 1 "C" Status register
DMA 1 "D" Buffer Descriptor Pointer register
DMA 1 "D" Control register
DMA 1 "D" Status register
DMA 2 Buffer Descriptor Pointer register
DMA 2 Control register
DMA 2 Status register
DMA 3 Buffer Descriptor Pointer register
DMA 3 Control register
DMA 3 Status register
DMA 4 Buffer Descriptor Pointer register
DMA 4 Control register
DMA 4 Status register
DMA 5 Buffer Descriptor Pointer register
DMA 5 Control register
DMA 5 Status register
DMA 6 Buffer Descriptor Pointer register
DMA 6 Control register
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7