Ethernet General Control Register (Egcr) Bit Definitions - Digi NS7520B-1-C36 Hardware Reference Manual

E F E c o n f i g u r a t i o n

Ethernet General Control register (EGCR) bit definitions

Address: FF80 0000
General information
These fields should be set only once, on device open:
ERX
ERXDMA
ERXLNG
ERXSHT
ERXBAD
These fields are used only when using Ethernet receive in interrupt service mode
rather than DMA mode (DMA interface logic). DMA mode provides higher performance
out of the Ethernet chip, and can be turned on and off.
ERXREG
ERFIFOH
ERXBR
31 30
ERX
ERX
DMA
15 14
MODE
Register bit assignment
Note:
1 5 8
ETX
ETXDMA
ETXWM
EFULLD
ETXREG
ETFIFOH
ETXBC
29 28 27 26
ERX ERX ERX ER
LNG SHT REG FIFOH
13 12 11 10
RXC TXC MAC_
Rsvd pNA
INV INV RESET
Bits D15:D00 are media control bits, with D07:D00 used in ENDEC mode
only.
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
25 24 23 22 21
ERX ETX
ERX
ETX ETXWM
BR BAD DMA
9 8 7 6 5
ITXA PDN:, AUI_TP:, LNK_DIS:, LPBK:, UTP_STP
20 19 18 17 16
ETX E
ET ETX
REG FIFOH BC FULLD
4 3 2 1 0
EXINT