Digi NS9215 Manuals

Manuals and User Guides for Digi NS9215. We have 1 Digi NS9215 manual available for free PDF download: Hardware Reference Manual

Digi NS9215 Hardware Reference Manual (517 pages)

Digi International Processor Hardware Reference

Brand: Digi | Category: Computer Hardware | Size: 2 MB

Hardware Reference
1
Chapter 9 : I / O H U B M O D U L

3
Chapter 1 5 : a N a L O G - T O - D I G I T a L C O N V E R T E R ( a D C ) M O D U L

3
- Table of Contents
  5
Chapter 1 2 : S E R I a L C O N T R O L M O D U L E : S P

3
Chapter 1 1 : S E R I a L C O N T R O L M O D U L E : H D L

5
Chapter 1 0 : S E R I a L C O N T R O L M O D U L E : U a R

5
Chapter 8 : a E S D a T a E N C R y P T I O N / D E C R y P T I O N M O D U L

5
Chapter 1 3 : I 2 C M a S T E R / S L a V E I N T E R F a C

7
Chapter 1 : P I N O U T ( 2 6 5 )

27
- The Legend
  27
- Memory Bus Interface
  28
- Ethernet Interface MAC
  30
- General Purpose I/O (GPIO)
  31
- System Clock
  43
  - System Clock Drawing
    44
  - RTC Clock and Battery Backup Drawing
    45
- System Mode
  45
- System Reset
  47
- JTAG Test
  48
- Adc
  49
- POR and Battery-Backed Logic
  50
- Power and Ground
  51
Chapter 2 : I / O C O N T R O L M O D U L E

53
Chapter 3 : Working with the CPU

82
- Instruction Sets
  82
  - ARM Instruction Set
    82
  - Thumb Instruction Set
    82
  - Java Instruction Set
    83
- System Control Processor (CP15) Registers
  83
  - ARM926EJ-S System Addresses
    83
  - Address Manipulation Example
    83
  - Accessing CP15 Registers
    83
  - Terms and Abbreviations
    84
  - Register Summary
    85
- R0: ID Code and Cache Type Status Registers
  86
  - R0: ID Code
    86
  - R0: Cache Type Register
    86
  - Cache Type Register and Field Description
    87
  - Dsize and Isize Fields
    87
- R1: Control Register
  88
  - Control Register
    89
  - Bit Functionality
    89
  - Icache and Dcache Behavior
    90
- R2: Translation Table Base Register
  91
  - Register Format
    91
- R3:Domain Access Control Register
  91
  - Access Permissions and Instructions
    91
- R4 Register
  92
- R5: Fault Status Registers
  92
  - Access Instructions
    92
  - Register Format
    92
  - Register Bits
    92
  - Status and Domain Fields
    93
- R6: Fault Address Register
  93
  - Access Instructions
    93
- R7:Cache Operations Register
  94
  - Write Instruction
    94
  - Cache Functions
    94
  - Cache Operation Functions
    95
  - Modified Virtual Address Format (MVA)
    96
  - Set/Way Format
    96
  - Set/Way Example
    96
  - Test and Clean Dcache Instructions
    96
  - Test, Clean, and Invalidate Dcache Instruction
    97
- R8:TLB Operations Register
  97
- R9: Cache Lockdown Register
  98
- R10:TLB Lockdown Register
  101
  - Register Format
    101
  - P Bit
    101
  - Invalidate Operation
    101
  - Programming Instructions
    102
  - Sample Code Sequence
    102
- R11 and R12 Registers
  102
- R13:Process ID Register
  102
  - FCSE PID Register
    103
  - Access Instructions
    103
  - Register Format
    103
  - Performing a Fast Context Switch
    103
  - Context ID Register
    104
  - Access Instructions
    104
  - Register Format
    104
- R14 Register
  104
- R15: Test and Debug Register
  104
- Jazelle(Java)
  104
- Dsp
  105
- Memorymanagement Unit (MMU)
  105
  - MMU Features
    105
  - Access Permissions and Domains
    106
  - Translated Entries
    106
  - MMU Program Accessible Registers
    107
  - Address Translation
    107
  - Translation Table Base
    108
  - TTB Register Format
    108
  - Table Walk Process
    109
  - First-Level Fetch
    109
  - First-Level Fetch Concatenation and Address
    110
  - First-Level Descriptor
    110
  - Page Table Descriptors
    110
  - First-Level Descriptor Bit Assignments: Priority Encoding of Fault Status
    111
  - First-Level Descriptor Bit Assignments: Interpreting First Level Descriptor Bits [1:0]
    111
  - Section Descriptor
    111
  - Section Descriptor Format
    111
  - Section Descriptor Bit Description
    112
  - Coarse Page Table Descriptor
    112
  - Coarse Page Table Descriptor Format
    112
  - Coarse Page Table Descriptor Bit Description
    112
  - Fine Page Table Descriptor
    112
  - Fine Page Table Descriptor Format
    113
  - Fine Page Table Descriptor Bit Description
    113
  - Translating Section References
    113
  - Second-Level Descriptor
    114
  - Second-Level Descriptor Format
    114
  - Second-Level Descriptor Bit Assignments
    115
  - Second-Level Descriptor Least Significant Bits
    115
  - Translation Sequence for Large
    116
  - Translating Sequence for Small
    117
  - Translation Sequence for Tiny
    118
  - Subpages
    118
- MMU Faults and CPU Aborts
  119
  - Alignment Fault Checking
    119
  - Fault Address and Fault Status Registers
    119
  - Priority Encoding Table
    120
  - Fault Address Register (FAR)
    120
  - FAR Values for Multi-Word Transfers
    120
  - Compatibility Issues
    121
- Domain Access Control
  121
  - Specifying Access Permissions
    121
  - Interpreting Access Permission Bits
    121
- Fault Checking Sequence
  122
  - Alignment Faults
    123
  - Translation Faults
    124
  - Domain Faults
    124
  - Permission Faults
    124
- External Aborts
  125
- Enabling and Disabling the MMU
  125
  - Enabling the MMU
    125
  - Disabling the MMU
    126
- TLB Structure
  126
- Caches and Write Buffer
  127
  - Cache Features
    127
  - Write Buffer
    128
  - Enabling the Caches
    128
  - Icache I and M Bit Settings
    129
  - Icache Page Table C Bit Settings
    129
  - R1 Register C and M Bits for Dcache
    129
  - Dcache Page Table C and B Settings
    129
- Cache MVA and Set/Way Formats
  130
- Noncachable Instruction Fetches
  133
  - Self-Modifying Code
    133
  - AHB Behavior
    134
  - Instruction Memory Barrier
    134
  - IMB Operation
    134
  - Sample IMB Sequences
    135
  - Features
    137
Chapter 4 : System Control Module

137
- Bus Interconnection
  137
- System Bus Arbiter
  138
  - High Speed Bus System
    138
  - High-Speed Bus Arbiters
    138
  - How the Bus Arbiter Works
    138
  - Ownership
    139
  - Locked Bus Sequence
    139
  - Relinquishing the Bus
    139
  - SPLIT Transfers
    140
  - Arbiter Configuration Example
    140
- Address Decoding
  141
- Programmable Timers
  142
  - Software Watchdog Timer
    142
- General Purpose Timers/Counters
  143
  - Source Clock Frequency
    143
  - GPTC Characteristics
    143
  - Control Field
    143
  - 16-Bit Mode Options
    144
- Basic PWM Function
  144
  - Functional Block Diagram
    144
- Enhanced PWM Function
  145
  - Sample Enhanced PWM Waveform
    145
- Quadrature Decoder Function
  145
- How the Quadrature Decoder/Counter Works
  146
  - Provides Input Signals
    146
  - Monitors How Far the Encoder Has Moved
    147
  - Digital Filter
    147
  - Testing Signals
    147
  - Timer Support
    147
- Interrupt Controller
  148
  - FIQ Interrupts
    148
  - IRQ Interrupts
    148
  - 32-Vector Interrupt Controller
    148
  - IRQ Characteristics
    149
  - Interrupt Sources
    149
- Vectored Interrupt Controller (VIC) Flow
  151
- Configurable System Attributes
  151
- PLL Configuration
  151
  - PLL Configuration and Control System Block Diagram
    152
- Bootstrap Initialization
  152
  - Configuring the Powerup Settings
    152
- System Configuration Registers
  154
  - Register Address Map
    154
- General Arbiter Control Register
  158
- BRC0, BRC1, BRC2, and BRC3 Registers
  158
  - Channel Allocation
    159
- AHB Error Detect Status 1
  159
- AHB Error Detect Status 2
  160
- AHB Error Monitoring Configuration Register
  161
- Timer Master Control Register
  162
- Timer 0-4 Control Registers
  164
- Timer 5 Control Register
  166
- Timer 6-9 Control Registers
  168
- Timer 6-9 High Registers
  170
- Timer 6-9 Low Registers
  171
- Timer 6-9 High and Low Step Registers
  172
- Timer 6-9 Reload Step Registers
  172
- Timer 0-9 Reload Count and Compare Register
  173
- Timer 0-9 Read and Capture Register
  174
- Interrupt Vector Address Register Level 31-0
  175
- Int (Interrupt) Config (Configuration) 31-0 Registers
  175
  - Individual Register Mapping
    175
- ISADDR Register
  176
- Interrupt Status Active
  177
- Interrupt Status Raw
  178
- Software Watchdog Configuration
  178
- Software Watchdog Timer
  179
- Clock Configuration Register
  180
- Module Reset Register
  182
- Miscellaneous System Configuration and Status Register
  184
- PLL Configuration Register
  186
  - PLL Frequency Formula
    186
- Active Interrupt Level ID Status Register
  187
- Power Management
  187
- AHB Bus Activity Status
  190
- System Memory Chip Select 0 Dynamic Memory Base and Mask Registers
  190
- System Memory Chip Select 1 Dynamic Memory Base and Mask Registers
  191
- System Memory Chip Select 2 Dynamic Memory Base and Mask Registers
  192
- System Memory Chip Select 3 Dynamic Memory Base and Mask Registers
  193
- System Memory Chip Select 0 Static Memory Base and Mask Registers
  194
- System Memory Chip Select 1 Static Memory Base and Mask Registers
  195
- System Memory Chip Select 2 Static Memory Base and Mask Registers
  196
- System Memory Chip Select 3 Static Memory Base and Mask Registers
  197
- Gen ID Register
  198
- External Interrupt 0-3 Control Register
  199
- RTC Module Control Register
  200
  - Features
    203
  - Memory Controller
    203
Chapter 5 : Memory Controller

204
Chapter 6 : Ethernet Communication Module

261
- Features
  261
- Common Acronyms
  261
- Ethernet Communications Module
  262
- Ethernet MAC
  262
  - MAC Module Block Diagram
    263
  - MAC Module Features
    263
  - PHY Interface Mappings
    264
- Station Address Logic (SAL)
  264
  - MAC Receiver
    265
- Statistics Module
  265
- Ethernet Front-End Module
  266
  - Ethernet Front-End Module (EFE)
    266
  - Receive Packet Processor
    266
  - Transmit Packet Processor
    267
- Receive Packet Processor
  267
- Transmit Packet Processor
  269
  - Transmit Buffer Descriptor Format
    270
  - Transmit Buffer Descriptor Field Definitions
    270
  - Transmitting a Frame
    271
  - Frame Transmitted Successfully
    272
  - Frame Transmitted Unsuccessfully
    272
  - Transmitting a Frame to the Ethernet MAC
    272
  - Ethernet Underrun
    272
- Ethernet Slave Interface
  273
- Interrupts
  273
  - Interrupt Sources
    273
  - Status Bits
    274
- Resets
  274
- Multicast Address Filtering
  275
  - Filter Entries
    275
  - Multicast Address Filter Registers
    275
  - Multicast Address Filtering Example 1
    275
  - Multicast Address Filtering Example 2
    276
  - Notes
    276
- Clock Synchronization
  276
  - Writing to Other Registers
    276
- Ethernet Control and Status Registers
  277
  - Register Address Filter
    277
- Ethernet General Control Register #1
  279
- Ethernet General Control Register #2
  282
- Ethernet General Status Register
  283
- Ethernet Transmit Status Register
  284
- Ethernet Receive Status Register
  286
- MAC Configuration Register #1
  288
- MAC Configuration Register #2
  289
  - PAD Operation Table for Transmit Frames
    291
- Back-To-Back Inter-Packet-Gap Register
  291
- Non Back-To-Back Inter-Packet-Gap Register
  292
- Collision Window/Retry Register
  293
- Maximum Frame Register
  294
- MII Management Configuration Register
  295
  - Clocks Field Settings
    296
- MII Management Command Register
  296
- MII Management Address Register
  297
- MII Management Write Data Register
  298
- MII Management Read Data Register
  298
- MII Management Indicators Register
  299
- Station Address Registers
  300
- Station Address Filter Register
  301
- Registerhash Tables
  302
  - Ht1
    302
  - Ht2
    303
- Statistics Registers
  303
- RX_A Buffer Descriptor Pointer Register
  315
- RX_B Buffer Descriptor Pointer Register
  315
- RX_C Buffer Descriptor Pointer Register
  316
- RX_D Buffer Descriptor Pointer Register
  316
- Ethernet Interrupt Status Register
  317
- Ethernet Interrupt Enable Register
  319
- TX Buffer Descriptor Pointer Register
  320
- Transmit Recover Buffer Descriptor Pointer Register
  321
- TX Error Buffer Descriptor Pointer Register
  321
- TX Stall Buffer Descriptor Pointer Register
  322
- RX_A Buffer Descriptor Pointer Offset Register
  323
- RX_B Buffer Descriptor Pointer Offset Register
  324
- RX_C Buffer Descriptor Pointer Offset Register
  324
- RX_D Buffer Descriptor Pointer Offset Register
  325
- Transmit Buffer Descriptor Pointer Offset Register
  325
- RX Free Buffer Register
  326
- Multicast Address Filter Registers
  327
- Multicast Address Mask Registers
  329
- Multicast Address Filter Enable Register
  331
- TX Buffer Descriptor RAM
  332
  - Offset+0
    332
  - Offset+4
    333
  - Offset+8
    333
  - Offset+C
    333
- Rx Fifo Ram
  333
- Sample Hash Table Code
  334
Chapter 7 : External DMA

339
- DMA Transfers
  339
  - Initiating DMA Transfers
    339
  - Processor-Initiated
    339
  - External Peripheral-Initiated
    339
- DMA Buffer Descriptor
  340
  - DMA Buffer Descriptor Diagram
    340
  - Source Address [Pointer]
    340
    
    Buffer Length
    340
    
    Destination Address [Pointer]
    340
    
    Status
    341
    
    Wrap (W) Bit
    341
    
    Interrupt (I) Bit
    341
    
    Last (L) Bit
    341
    
    Full (F) Bit
    341
  - Descriptor List Processing
    341
  - Peripheral DMA Read Access
    342
    
    Determining the Width of PDEN
    342
    
    Equation Variables
    342
    
    Peripheral DMA Single Read Access
    343
    
    Peripheral DMA Burst Read Access
    343
  - Peripheral DMA Write Access
    343
    
    Determining the Width of PDEN
    344
    
    Peripheral DMA Single Write Access
    344
    
    Peripheral DMA Burst Write Access
    344
  - Peripheral REQ and DONE Signaling
    344
    
    REQ Signal
    344
    
    DONE Signal
    345
    
    Special Circumstances
    345
  - Static RAM Chip Select Configuration
    345
  - Control and Status Registers
    346
    
    Register Address Map
    346
  - DMA Buffer Descriptor Pointer
    346
  - DMA Control Register
    347
  - DMA Status and Interrupt Enable Register
    350
  - DMA Peripheral Chip Select Register
    352
    
    Features
    355
    
    Block Diagram
    356
    
    Data Blocks
    356
  - AES DMA Buffer Descriptor
    356
    
    AES Buffer Descriptor Diagram
    357
    
    Source Address [Pointer]
    357
    
    Source Buffer Length
    357
    
    Destination Buffer Length
    357
    
    Destination Address [Pointer]
    357
    
    AES Control
    357
    
    AES Op Code
    358
    
    WRAP (W) Bit
    358
    
    Interrupt (I) Bit
    358
    
    Last (L) Bit
    358
    
    Full (F) Bit
    358
  - Decryption
    359
  - ECB Processing
    359
    
    Processing Flow Diagram
    359
  - CBC, CFB, OFB, and CTR Processing
    360
    
    Processing Flow Diagram
    360
  - CCM Mode
    360
    
    Nonce Buffer
    361
    
    Processing Flow
    361
    
    Block Diagram
    364
    
    AHB Slave Interface
    364
  - DMA Controller
    364
    
    Servicing RX and Fifos
    364
    
    Buffer Descriptors
    365
    
    Source Address [Pointer]
    365
    
    Buffer Length
    365
    
    Control[15] - W
    365
    
    Control[14] - I
    365
    
    Control[13] - L
    365
    
    Control[12] - F
    365
    
    Control[11:0]
    366
    
    Status[15:0]
    366
  - Transmit DMA Example
    367
    
    Process
    367
    
    Visual Example
    368
  - Control and Status Register Address Maps
    368
    
    UART a Register Address Map
    369
    
    UART B Register Address Map
    369
    
    UART C Register Address Map
    370
    
    UART D Register Address Map
    370
    
    SPI Register Address Map
    371
    
    AD Register Address Map
    371
    
    Reserved
    371
    
    I2C Register Address Map
    371
    
    RTC Register Address Map
    372
    
    IO Hardware Assist Register Address Map (0)
    372
    
    IO Hardware Assist Register Address Map (1)
    372
    
    IO Register Address Map (0)
    372
    
    IO Register Address Map (1)
    372
  - [Module] Interrupt and FIFO Status Register
    372
  - [Module] DMA RX Control
    375
  - [Module] DMA RX Buffer Descriptor Pointer
    376
  - [Module] RX Interrupt Configuration Register
    377
  - [Module] Direct Mode RX Status FIFO
    378
  - [Module] Direct Mode RX Data FIFO
    379
  - [Module] DMA TX Control
    380
  - [Module] DMA TX Buffer Descriptor Pointer
    381
  - [ M O D U L E ] T X I N T E R R U P T C O N F I G U R a T I O N R E G I S T E R
    381
  - [Module] Direct Mode TX Data FIFO
    382
  - [Module] Direct Mode TX Data Last FIFO
    383
    
    Features
    385
    
    UART Module Structure
    386
  - Normal Mode Operation
    386
    
    Example Configuration
    386
  - Baud Rate Generator
    387
    
    Baud Rates
    387
  - Hardware-Based Flow Control
    388
  - Character-Based Flow Control (XON/XOFF)
    388
    
    Example Configuration
    388
  - Forced Character Transmission
    388
    
    Force Character Transmission Procedure
    389
    
    Collecting Feedback
    389
  - ARM Wakeup on Character Recognition
    389
    
    Example Configuration
    389
  - Wrapper Control and Status Registers
    390
    
    Register Address Map
    390
  - Wrapper Configuration Register
    391
  - Interrupt Enable Register
    393
  - Interrupt Status Register
    395
  - Receive Character GAP Control Register
    398
  - Receive Buffer GAP Control Register
    399
  - Receive Character Match Control Register
    399
  - Receive Character-Based Flow Control Register
    400
  - Force Transmit Character Control Register
    402
  - ARM Wakeup Control Register
    403
  - Transmit Byte Count
    404
  - UART Receive Buffer
    405
  - UART Transmit Buffer
    405
  - UART Baud Rate Divisor LSB
    406
  - UART Baud Rate Divisor MSB
    406
  - UART Interrupt Enable Register
    407
  - UART Interrupt Identification Register
    408
  - UART FIFO Control Register
    409
  - UART Line Control Register
    409
  - UART Modem Control Register
    411
  - UART Line Status Register
    411
  - UART Modem Status Register
    412
    
    HDLC Module Structure
    415
  - Receive and Transmit Operations
    415
    
    Receive Operation
    416
    
    Transmit Operation
    416
    
    Transmitter Underflow
    416
  - Clocking
    416
  - Bits
    416
    
    Last Byte Bit Pattern Table
    417
  - Data Encoding
    417
    
    Encoding Examples
    417
  - Digital Phase-Locked-Loop (DPLL) Operation: Encoding
    418
    
    Transitions
    418
    
    DPLL-Tracked Bit Cell Boundaries
    419
    
    NRZ and NRZI Data Encoding
    419
    
    Biphase Data Encoding
    419
  - DPLL Operation: Adjustment Ranges and Output Clocks
    419
    
    NRZ and NRZI Encoding
    420
    
    Biphase-Level Encoding
    420
    
    Biphase-Mark and Biphase-Space Encoding
    421
    
    IRDA-Compliant Encode
    421
  - Normal Mode Operation
    421
    
    Example Configuration
    421
  - Wrapper and HDLC Control and Status Registers
    422
    
    Register Address Map
    422
  - Wrapper Configuration Register
    422
  - Interrupt Enable Register
    424
  - Interrupt Status Register
    425
  - HDLC Data Register 1
    427
  - HDLC Data Register 2
    427
  - HDLC Data Register 3
    428
  - HDLC Control Register 1
    429
  - HDLC Control Register 2
    429
  - HDLC Clock Divider Low
    430
  - HDLC Clock Divider High
    431
    
    Features
    433
    
    SPI Module Structure
    434
  - SPI Controller
    434
    
    Simple Parallel/Serial Data Conversion
    434
    
    Full Duplex Operation
    434
  - SPI Clocking Modes
    435
    
    Timing Modes
    435
    
    Clocking Mode Diagrams
    435
  - SPI Clock Generation
    436
    
    Clock Generation Samples
    436
    
    In SPI Master Mode
    436
    
    In SPI Slave Mode
    436
  - System Boot-Over-SPI Operation
    436
    
    Available Strapping Options
    437
    
    EEPROM/FLASH Header
    437
    
    Header Format
    437
    
    Time to Completion
    438
  - SPI Control and Status Registers
    439
    
    Register Address Map
    439
  - SPI Configuration Register
    439
  - Clock Generation Register
    440
    
    Register Programming Steps
    441
  - Interrupt Enable Register
    441
  - Interrupt Status Register
    442
  - SPI Timing Characteristics
    443
    
    SPI Master Timing Diagram
    444
    
    SPI Slave Timing Parameters
    444
    
    SPI Slave Timing Diagram
    445
    
    Overview
    447
  - Physical I2C Bus
    447
    
    Multi-Master Bus
    448
  - I2C External Addresses
    448
  - I2C Command Interface
    449
    
    Locked Interrupt Driven Mode
    449
    
    Master Module and Slave Module Commands
    449
    
    Bus Arbitration
    449
  - I2C Registers
    450
    
    Register Address Map
    450
  - Command Transmit Data Register
    450
    
    Register
    450
    
    Register Bit Assignment
    451
  - Status Receive Data Register
    451
    
    Register
    451
  - Master Address Register
    452
    
    Register
    452
    
    Register Bit Assignment
    453
  - Slave Address Register
    453
    
    Register
    453
  - Configuration Register
    454
    
    Timing Parameter for Fast-Mode
    454
    
    Register
    454
    
    Register Bit Assignment
    454
  - Interrupt Codes
    455
    
    Master/Slave Interrupt Codes
    455
  - Software Driver
    456
    
    I2C Master Software Driver
    456
    
    I2C Slave High Level Driver
    456
  - Flow Charts
    457
    
    Master Module (Normal Mode, 16-Bit)
    457
    
    Slave Module (Normal Mode, 16-Bit)
    458
    
    RTC Functionality
    459
Chapter 14 : Real Time Clock Module

460
- RTC Configuration and Status Registers
  460
  - Register Address Map
    460
- RTC General Control Register
  460
- 12/24 Hour Register
  461
- Time Register
  462
- Calendar Register
  463
- Time Alarm Register
  464
- Calendar Alarm Register
  465
- Alarm Enable Register
  465
- Event Flags Register
  466
- Interrupt Enable Register
  468
- Interrupt Disable Register
  469
- Interrupt Enable Status Register
  470
- General Status Register
  471
  - Features
    473
  - ADC Module Structure
    473
  - ADC Control Block
    474
- ADC DMA Procedure
  474
- ADC Control and Status Registers
  475
  - Register Address Map
    475
- ADC Configuration Register
  475
- ADC Clock Configuration Register
  477
- ADC Output Registers 0-7
  477
Chapter 16 : Timing

479
- Electrical Characteristics
  479
  - Absolute Maximum Ratings
    479
  - Recommended Operating Conditions
    480
  - Power Dissipation
    480
- DC Electrical Characteristics
  481
  - Inputs
    481
  - Ouputs
    482
- Reset and Edge Sensitive Input Timing Requirements
  482
- Memory Timing
  484
  - SDRAM Burst Read (16-Bit)
    485
  - SDRAM Burst Read (16 Bit), CAS Latency = 3
    486
  - SDRAM Burst Write (16 Bit)
    487
  - SDRAM Burst Read (32 Bit)
    488
  - SDRAM Burst Read (32 Bit), CAS Latency = 3
    489
  - SDRAM Burst Write (32-Bit)
    490
  - SDRAM Load Mode
    491
  - SDRAM Refresh Mode
    492
  - Clock Enable Timing
    493
  - Values in SRAM Timing Diagrams
    494
  - Static RAM Read Cycles with 0 Wait States
    495
  - Static RAM Asynchronous Page Mode Read, WTPG = 1
    496
  - Static RAM Read Cycle with Configurable Wait States
    497
  - Static RAM Sequential Write Cycles
    498
  - Static RAM Write Cycle
    499
  - Static Write Cycle with Configurable Wait States
    500
  - Slow Peripheral Acknowledge Timing
    501
  - Slow Peripheral Acknowledge Read
    502
  - Slow Peripheral Acknowledge Write
    502
  - Ethernet Timing
    503
  - Ethernet MII Timing
    503
  - I 2 C Timing
    504
  - SPI Timing
    505
  - SPI Master Mode 0 and 1: 2-Byte Transfer
    507
  - SPI Master Mode2 and 3: 2-Byte Transfer
    507
  - SPI Slave Mode 0 and 1: 2-Byte Transfer
    508
  - SPI Slave Mode 2 and 3: 2-Byte Transfer
    508
- Reset and Hardware Strapping Timing
  509
- JTAG Timing
  510
- Clock Timing
  511
  - System PLL Reference Clock Timing
    511
Chapter 17 : Packaging

513
- Package
  513
- Processor Dimensions
  514
Chapter 18 : Change Log

517
- Revision B
  517
- Revision C
  517

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Digi NS9215 Hardware Reference Manual (517 pages)

Table of Contents

Chapter 9 : I / O H U B M O D U L

Chapter 1 5 : a N a L O G - T O - D I G I T a L C O N V E R T E R ( a D C ) M O D U L

Chapter 1 2 : S E R I a L C O N T R O L M O D U L E : S P

Chapter 1 1 : S E R I a L C O N T R O L M O D U L E : H D L

Chapter 1 0 : S E R I a L C O N T R O L M O D U L E : U a R

Chapter 8 : a E S D a T a E N C R y P T I O N / D E C R y P T I O N M O D U L

Chapter 1 3 : I 2 C M a S T E R / S L a V E I N T E R F a C

Chapter 1 : P I N O U T ( 2 6 5 )

Chapter 2 : I / O C O N T R O L M O D U L E

Chapter 3 : Working with the CPU

Chapter 4 : System Control Module

Chapter 5 : Memory Controller

Chapter 6 : Ethernet Communication Module

Chapter 7 : External DMA

Chapter 14 : Real Time Clock Module

Chapter 16 : Timing

Chapter 17 : Packaging

Chapter 18 : Change Log

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