Digi NS7520B-1-C36 Hardware Reference Manual page 32

P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s
Mnemonic
COL
CRS
RXCLK
RXD3
RXD2
RXD1
RXD0
RXER
RXDV
Table 7: Ethernet interface MAC signal description
2 0
Signal
Transmit collision
Receive carrier sense
Receive clock
Receive data signals
Receive error
Receive data valid
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Description
Input signal asserted by the external Ethernet PHY when a
collision is detected.
Asserted by the external Ethernet PHY whenever the
receive medium is non-idle.
An input to the NS7520 from the external PHY module.
The receive clock provides the synchronous data clock for
receive data.
Nibble bus used by the NS7520 to input receive data from
the external Ethernet PHY. All receive data signals are
synchronized to RXCLK.
In ENDEC mode, only RXD0 is used for receive data.
Input asserted by the external Ethernet PHY when the
Ethernet PHY encounters invalid symbols from the
network.
Input asserted by the external Ethernet PHY when the PHY
drives valid data on the RXD inputs.