Single Cycle Read/Write - Digi NS7520B-1-C36 Hardware Reference Manual

F P / E D O D R A M c o n t r o l l e r
Normal and burst (FP/EDO) cycles
Programmable wait states for normal (also first cycle ion burst access) and
burst cycles
Programmable base address and chip select size

Single cycle read/write

Figure 9 shows FP DRAM normal read and write cycles.
BCLK
ADDR
R/W_
RAS_
DADDR
CAS_
WE_
OE_
DATA
TA_
Figure 9: Normal FP DRAM bus cycles
All DRAM cycles must operate a minimum of 1 wait state. (If the controller is
programmed for 0 wait states, operation is unpredictable). A single wait state DRAM
cycle requires the DRAM devices to tolerate a single BCLK cycle for RAS precharge
and CAS access timing.
The CAS_ signal is deasserted on the rising edge in which TA_ is recognized.
The RAS_ signal is deasserted on the falling edge of BCLK after CAS_ is
asserted.
Important:
1 1 0
T1 TW TW T2
FP DRAM Write
You cannot set the PS field to
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
T1 TW TW T2
FP DRAM Read
for FP DRAM.
2'b11
T1 TW