Digi Rabbit 5000 User Manual

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Rabbit® 5000 Microprocessor

User's Manual

019-0168_E

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Page 1 Rabbit® 5000 Microprocessor User’s Manual 019-0168_E...
Page 2: Rabbit 5000 Microprocessor User's Manual
Rabbit 5000 Microprocessor User’s Manual Part Number 019-0168 • Printed in the U.S.A. Digi International Inc. © 2013 • All rights reserved. Digi International Inc. reserves the right to make changes and improvements to its products without providing notice. Trademarks ®...
Page 3: Table Of Contents
ABLE OF ONTENTS Chapter 1. The Rabbit 5000 Processor 1.1 Introduction............................13 1.2 Features ...............................14 1.3 Block Diagram ............................16 1.4 Basic Specifications ..........................17 1.5 Comparing Rabbit Microprocessors ....................18 Chapter 2. Clocks 2.1 Overview.............................21 2.1.1 Block Diagram ...........................22 2.1.2 Registers .............................22 2.2 Dependencies ............................23 2.2.1 I/O Pins ............................23...
Page 4 8.1.2 Registers ............................ 89 8.2 Dependencies ............................. 90 8.2.1 I/O Pins ............................90 8.2.2 Clocks ............................90 8.2.3 Other Registers .......................... 90 8.2.4 Interrupts ............................ 90 8.3 Operation ............................90 8.4 Register Descriptions ......................... 91 Rabbit 5000 Microprocessor User’s Manual...
Page 5 Chapter 9. Parallel Port B 9.1 Overview.............................93 9.1.1 Block Diagram ...........................94 9.1.2 Registers .............................94 9.2 Dependencies ............................94 9.2.1 I/O Pins ............................94 9.2.2 Clocks ............................94 9.2.3 Other Registers ...........................94 9.2.4 Interrupts ............................95 9.3 Operation ............................95 9.4 Register Descriptions ..........................95 Chapter 10. Parallel Port C 10.1 Overview............................97 10.1.1 Block Diagram .........................98 10.1.2 Registers ...........................98...
Page 6 17.2 Dependencies ..........................175 17.2.1 I/O Pins ..........................175 17.2.2 Clocks ............................ 175 17.2.3 Other Registers ........................176 17.2.4 Interrupts ..........................176 17.3 Operation ............................177 17.3.1 Asynchronous Mode ......................177 17.3.2 Clocked Serial Mode ......................178 Rabbit 5000 Microprocessor User’s Manual...
Page 7 17.4 Register Descriptions ........................180 Chapter 18. Serial Ports E – F 18.1 Overview............................187 18.1.1 Block Diagram ........................188 18.1.2 Registers ..........................189 18.2 Dependencies ..........................190 18.2.1 I/O Pins ..........................190 18.2.2 Clocks .............................190 18.2.3 Other Registers ........................190 18.2.4 Interrupts ..........................191 18.3 Operation ............................192 18.3.1 Asynchronous Mode ......................192 18.3.2 HDLC Mode ..........................192 18.3.3 More on Clock Synchronization and Data Encoding .............193...
Page 8 24.2.2 Clocks ............................ 290 24.2.3 Other Registers ........................290 24.2.4 Interrupts ..........................290 24.3 Operation ............................291 24.3.1 Input-Capture Channel ......................291 24.3.2 Handling Interrupts ........................ 291 24.3.3 Example ISR .......................... 291 24.3.4 Capture Mode ........................292 Rabbit 5000 Microprocessor User’s Manual...
Page 9 24.3.5 Count Mode ..........................292 24.4 Register Descriptions ........................293 Chapter 25. Quadrature Decoder 25.1 Overview............................299 25.1.1 Block Diagram ........................301 25.1.2 Registers ..........................301 25.2 Dependencies ..........................302 25.2.1 I/O Pins ..........................302 25.2.2 Clocks .............................302 25.2.3 Other Registers ........................302 25.2.4 Interrupts ..........................302 25.3 Operation ............................303 25.3.1 Handling Interrupts ........................303 25.3.2 Example ISR ..........................303 25.4 Register Descriptions ........................304...
Page 10 32.1.3 Mechanical Dimensions and Land Pattern ................391 32.2 Rabbit Pin Descriptions........................393 Appendix A. Parallel Port Pins with Alternate Functions A.1 Alternate Parallel Port Pin Outputs ....................397 A.2 Alternate Parallel Port Pin Inputs....................399 Rabbit 5000 Microprocessor User’s Manual...
Page 11 Appendix B. Rabbit 5000 Errata B.1 Errata ..............................401 Index Table of Contents...
Page 12 Rabbit 5000 Microprocessor User’s Manual...
Page 13: Chapter 1. The Rabbit 5000 Processor
100 MHz, with compact code and support for up to 16 MB of memory. Operating with a 1.8 V core and 3.3 V I/O, the Rabbit 5000 boasts eight channels of DMA, six serial ports with IrDA, 48+ digital I/O, quadrature decoder, PWM outputs, and pulse capture and measurement capabilities.
Page 14: Features
128 KB of internal high-speed 16-bit SRAM, which can be used in addition to any external memory devices. A built-in slave port allows the Rabbit 5000 to be used as master or slave in multi-processor systems, permitting separate tasks to be assigned to dedicated processors. An 8-line data port and five control signals simplify the exchange of data between devices.
Page 15 Two external interrupt vectors can multiplex inputs from up to six external pins. The Rabbit 5000 has three timer systems. Timer A consists of ten 8-bit counters, each of which has a programmed time constant. Six of them can be cascaded from the primary Timer A counter.
Page 16: Block Diagram
1.3 Block Diagram battery- backable Rabbit 5000 Microprocessor User’s Manual...
Page 17: Basic Specifications
1.4 Basic Specifications Two versions of the Rabbit 5000 are available—the standard 289-ball BGA and a compact 196-ball BGA for specialty Wi-Fi applications. The larger package is intended for most Rabbit applications; the smaller package has specific features and limitations, and is not presently offered for sale.
Page 18: Comparing Rabbit Microprocessors
1.5 Comparing Rabbit Microprocessors The Rabbit 2000, Rabbit 3000, Rabbit 4000, and Rabbit 5000 features are compared below. Feature Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000 Maximum Clock Speed, industrial 100 MHz 60 MHz 55.5 MHz 30 MHz Maximum Clock Speed,...
Page 19 Clock Speed/8 Clock Speed/32 Rate Ethernet Port 10/100Base-T 10Base-T None None Wi-Fi PWM Outputs None Variable-Phase PWM Outputs None None (PPM) Input Capture Units None Quadrature Decoders 2 channels 2 channels 2 channels None Chapter 1 The Rabbit 5000 Processor...
Page 20 Rabbit 5000 Microprocessor User’s Manual...
Page 21: Chapter 2. Clocks
LOCKS 2.1 Overview The Rabbit 5000 supports up to three separate clocks at once—the main clock, the 32 kHz clock, and the 20 MHz Wi-Fi clock. The main clock is used to drive the processor clock and the peripheral clock inside the processor. The 32 kHz clock is used to drive the asyn- chronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers.
Page 22: Block Diagram
Register Name Mnemonic I/O Address Reset Global Control/Status Register GCSR 0x0000 11000000 Global Clock Modulator 0 Register GCM0R 0x000A 00000000 Global Clock Modulation 1 Register GCM1R 0x000B 00000000 Global Clock Double Register GCDR 0x000F 00000000 Rabbit 5000 Microprocessor User’s Manual...
Page 23: Dependencies
2.2 Dependencies 2.2.1 I/O Pins The main clock input is on the CLKI pin. There is an internal Schmitt trigger on this pin to mitigate any noise problems associated with slowly transitioning signals. The main clock disable output is on the CLKIEN pin. Its state is changed by one of the bit combinations of bits 4:2 in GCSR.
Page 24: Operation
When the 32 kHz clock is enabled in GCSR, it can be further divided by 2, 4, 6, or 8 to generate even lower frequencies by enabling those modes in bits 0–2 of GPSCR. See Table 2-4 for more details. Rabbit 5000 Microprocessor User’s Manual...
Page 25: Spectrum Spreader
2.3.2 Spectrum Spreader When enabled, the spectrum spreader stretches and compresses the main clock in a complex pattern that spreads the energy of the clock harmonics over a wider range of frequencies. Figure 2-1. Effects of Spectrum Spreader There are three settings that correspond to normal and strong spreading in the 0–50 MHz and >50 MHz main clock range.
Page 26 If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. Rabbit 5000 Microprocessor User’s Manual...
Page 27: Clock Doubler
2.3.3 Clock Doubler The clock doubler allows a lower frequency crystal to be used for the main oscillator and to provide an added range over which the clock frequency can be adjusted. The clock doubler is controlled via the Global Clock Double Register (GCDR). The clock doubler uses an on-chip delay circuit that must be programmed by the user at startup if there is a need to double the clock.
Page 28 4% variation in period on alternate clocks. The memory access time is not affected because the memory bus cycle is 2 clocks long and includes both a long and a short Rabbit 5000 Microprocessor User’s Manual...
Page 29 clock, resulting in no net change due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly The maximum allowed clock speed must be reduced slightly if the clock is supplied via the clock doubler.
Page 30: 32 Khz Clock
If these features are not used in a design, the use of the 32 kHz clock is optional. A simplified version of the recommended oscillator circuit for the Rabbit 5000 is shown below. The values of resistors and capacitors may need to be adjusted for various frequen- cies and crystal load capacitances.
Page 31 The 32 kHz oscillator can be used to drive the processor and the peripheral clock to provide significant power savings in “ultra-sleepy” modes. The 32 kHz oscillator can be divided by 2, 4, 8, or 16 to provide clock speeds as low as 2.048 kHz. Special self-timed chip selects are available to keep the memory devices enabled for as short a time as possible when an ultra-sleepy mode is enabled;...
Page 32: Register Descriptions
Processor clock from the main clock, divided by 6. Peripheral clock from the main clock, divided by 6. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 33 Global Clock Modulator 0 Register (GCM0R) (Address = 0x000A) Bit(s) Value Description Clock dither in 1 ns steps, from 0 ns to 26 ns. Do not modify while the dither function is enabled. Clock dither in 0.5 ns steps, from 0 ns to 13 ns. Clock dither in 2 ns steps, from 0 ns to 52 ns.
Page 34 20 ns nominal low time. 10001 3 ns nominal low time. 10010 4 ns nominal low time. 10011 5 ns nominal low time. other Any bit combination not listed is reserved and must not be used. Rabbit 5000 Microprocessor User’s Manual...
Page 35 Global Output Control Register (GOCR) (Address = 0x000E) Bit(s) Value Description CLK pin is driven with peripheral clock. CLK pin is driven with peripheral clock divided by 2. CLK pin is low. CLK pin is high. STATUS pin is active (low) during a first opcode byte fetch. STATUS pin is active (low) during an interrupt acknowledge.
Page 36 Rabbit 5000 Microprocessor User’s Manual...
Page 37: Chapter 3. Reset And Bootstrap 3.1 Overview
Serial Port A or the slave port. In this mode, bytes can be written to internal registers to set up the Rabbit 5000 for a particular configuration, or to memory to load a program. The processor can begin normal operation once the bootstrap operation is completed.
Page 38: Block Diagram
3.1.1 Block Diagram 3.1.2 Registers Register Name Mnemonic I/O Address Reset Slave Port Control Register SPCR 0x0024 0xx00000 Rabbit 5000 Microprocessor User’s Manual...
Page 39: Dependencies
SMODE0 and SMODE1 pins controls its operation. SYSCFG0 — When the Rabbit 5000 is first powered up or when it is reset, the state of this pin controls whether memory bank zero is mapped to /CS0 or the internal SRAM (/CS3).
Page 40: Operation
3.3 Operation Pulling the /RESET pin low will initialize everything in the Rabbit 5000 except for the real-time clock registers and the onchip-encryption RAM. The reset of the Rabbit 5000 is delayed until any write cycles in progress are completed; the reset takes effect as soon as no write cycles are occurring.
Page 41 Bootstrap from Serial Port A, serial flash mode. Bootstrap from Serial Port A, asynchronous mode. If both SMODE pins are zero, the Rabbit 5000 begins fetching instructions from the memory device mapped into memory bank 0. When SYSCFG0 is low, memory bank 0 is set to /CS0 and /OE0.
Page 42: Asynchronous Serial Bootstrap
Chip select (to serial flash) Serial clock (output to serial flash) The Rabbit 5000 divides the main clock by 64 to provide the SPI clock for the serial flash bootstrap. Once this mode is entered, the Rabbit 5000 will send the byte sequence "0x03 0x00 0x00 0x00", which is an industry-standard command that enables continuous read...
Page 43: Parallel Bootstrap
Figure 3-1. SPI Timing Diagram for Serial Flash Bootstrap Mode 3.3.3 Parallel Bootstrap When the parallel bootstrap mode is selected by the SMODE pins, the Rabbit 5000 will enable the parallel slave port interface on Parallel Ports A and B, and will wait for triplets to be sent to that interface.
Page 44: Register Descriptions
Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus. Slave port interrupts are disabled. Slave port interrupts use Interrupt Priority 1. Slave port interrupts use Interrupt Priority 2. Slave port interrupts use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 45: Chapter 4. System Management 4.1 Overview
The 48-bit width provides a 272-year span before rollover occurs. There are two watchdog timers in the Rabbit 5000, both clocked by the 32 kHz clock. The main watchdog timer can be set to time out from 250 ms to 2 seconds, and resets the pro- cessor if not reloaded within that time.
Page 46: Block Diagram
4.1.1 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 47: Registers
4.1.2 Registers Mnemonic I/O Address Register Name Reset Global Control/Status Register GCSR 0x0000 11000000 Real-Time Clock Control Register RTCCR 0x0001 00000000 Real-Time Clock Byte 0 Register RTC0R 0x0002 xxxxxxxx Real-Time Clock Byte 1 Register RTC1R 0x0003 xxxxxxxx Real-Time Clock Byte 2 Register RTC2R 0x0004 xxxxxxxx...
Page 48: Dependencies
The secondary watchdog interrupt will occur whenever the secondary watchdog is enabled and allowed to count down to zero. It is cleared by restarting the secondary watch- dog by writing to WDTCR. The secondary watchdog interrupt always occurs at Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 49: Operation
4.3 Operation 4.3.1 Periodic Interrupt The following steps explain how a periodic interrupt is used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Enable the periodic interrupt by writing to GCSR. 3. The interrupt request is cleared by reading from GCSR. A sample interrupt handler is shown below.
Page 50: Watchdog Timer
; determine why the interrupt occurred and take appropriate action ld a, 0x40 ; timeout period of 0x40/32kHz = 1.95ms ioi ld (SWDTR), a ; clear the interrupt request pop af ipres Rabbit 5000 Microprocessor User’s Manual...
Page 51: Register Descriptions
4.4 Register Descriptions Global Control/Status Register (GCSR) (Address = 0x0000) Bit(s) Value Description No reset or watchdog timer timeout since the last read. The watchdog timer timed out. These bits are cleared by a read of this register. (Read- only) This bit combination is not possible.
Page 52 Restart the watchdog timer with a 500 ms timeout period. 0x53 Restart the watchdog timer with a 250 ms timeout period. 0x5F Restart the secondary watchdog timer. other No effect on watchdog timer or secondary watchdog timer. Rabbit 5000 Microprocessor User’s Manual...
Page 53 Watchdog Timer Test Register (WDTTR) (Address = 0x0009) Bit(s) Value Description 0x51 Clock the least significant byte of the watchdog timer from the peripheral clock. 0x52 Clock the most significant byte of the watchdog timer from the peripheral clock. 0x53 Clock both bytes of the watchdog timer, in parallel, from the peripheral clock.
Page 54 Program fetch as a function of the SMODE pins. (Read- Ignore the SMODE pins program fetch function. only) Read These bits report the state of the SMODE pins. 00011 CPU identifier for this version of the chip. Rabbit 5000 Microprocessor User’s Manual...
Page 55 Battery-Backed Onchip-Encryption RAM (VRAM00) (Address = 0x0600) through through (VRAM31) (Address = 0x061F) Bit(s) Value Description General-purpose RAM locations. Cleared by Intrusion Detect conditions. Chapter 4 System Management...
Page 56 Rabbit 5000 Microprocessor User’s Manual...
Page 57: Chapter 5. Memory Management
16-bit mode allows 0 to 7 wait states depending on the settings. Both 8-bit and 16-bit page-mode devices are also supported. In addition, the Rabbit 5000 contains 128 KB of internal SRAM that resides on its own chip select signal. It can be enabled in either 8- or 16-bit mode.
Page 58 Figure 5-1. Mapping Rabbit 5000 Physical Memory Space Either one or both of the two most significant address bits (which are used to select the quadrant) can be inverted, providing the ability to bank-switch other pages from a larger memory device into the same memory bank.
Page 59 Figure 5-2. Logical and Physical Memory Mapping Chapter 5 Memory Management...
Page 60: Block Diagram
These two features allow both code and data to access separate 64 KB logical spaces instead of sharing a single space. It is possible to protect memory in the Rabbit 5000 at three different levels—each of the memory banks can be made read-only, physical memory can be write-protected in 64 KB blocks, and two of those 64 KB blocks can be protected with a granularity of 4 KB.
Page 61: Registers
5.1.2 Registers Register Name Mnemonic I/O Address Reset MMU Instruction/Data Register MMIDR 0x0010 00000000 Stack Segment Register STACKSEG 0x0011 00000000 Stack Segment LSB Register STACKSEGL 0x001A 00000000 Stack Segment MSB Register STACKSEGH 0x001B 00000000 Data Segment Register DATSEG 0x0012 00000000 Data Segment LSB Register DATSEGL 0x001E...
Page 62: Dependencies
The interrupt request is cleared when it is handled. The stack limit violation interrupt vector is in the IIR at offset 0x1B0. It is always set to Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 63: Operation
5.3 Operation 5.3.1 Memory Management Unit (MMU) Code execution takes place in the 64 KB logical memory space, which is divided into four segments: root, data, stack, and extended (XMEM). The root segment is always mapped starting at physical address 0x000000, but the other segments can be remapped to start at any physical 4 KB block boundary.
Page 64: Memory Bank Operation
Figure 5-3. MMU Operation 5.3.2 Memory Bank Operation On startup the Rabbit 5000 checks the status of the SYSCFG pins. To provide support for external memory, both SYSCFG pins should be set low and Memory Bank 0 enabled to use /CS0, /OE0, and /WE0 in 8-bit mode with four wait states and write protection enabled.
Page 65 The two address bits used to select the bank can be inverted in MBxCR, which enables mapping different sections of a memory device larger than the current memory bank into memory. Figure 5-4 shows an example of this feature. Figure 5-4. Mapping Different Sections of a Memory Device Larger Than the Current Memory Bank It is possible to extend the timing of the /OE and/or /WE strobes by one half of a clock.
Page 66: Memory Modes
5.3.3 Memory Modes The Rabbit 5000 supports both 8-bit and 16-bit memories on all chip selects, including the internal SRAM. It also provides support for page-mode devices. The mode for each chip select is set in MACR; 8-bit mode is the default for all chip selects.
Page 67 Page-Mode memories provide for a faster access time if the requested data are in the same page as the previous data. In the Rabbit 5000 (and most memory devices) a page can be selected as either 8 or 16 bytes. Thus, if an address is identical to the previous address except in the lower four bits, the access time is assumed to be faster.
Page 68: Separate Instruction And Data Space
This mapping will only occur when the RAMSR is within the root or data segments; the RAMSR will be ignored if it is mapped to the stack segment or XPC window. The Rabbit 5000 Designer’s Handbook provides further details on the use of the separate instruction and data space feature. 5.3.5 Memory Protection Memory blocks may be protected at three separate granularities, as shown in Table 5-4.
Page 69: Stack Protection
5.3.6 Stack Protection The Rabbit 5000 provides stack overflow and underflow protection. Low and high logical address limits can be set in STKLLR and STKHLR; a Priority 3 stack-violation interrupt occurs when a stack-based write occurs within the 16 bytes below the upper limit or within the 16 bytes above the lower limit.
Page 70: Register Descriptions
(Address = 0x0011) Bit(s) Value Description Read The current contents of this register are reported. Eight LSBs (MSBs are set to zero by write) of physical address offset to use if Write SEGSIZ[7:4]  Addr[15:12] < 0xE Rabbit 5000 Microprocessor User’s Manual...
Page 71 Stack Segment Low Register (STACKSEGL) (Address = 0x001A) Bit(s) Value Description Read The current contents of this register are reported. Eight LSBs of physical address offset to use if SEGSIZ[7:4]  Addr[15:12] < Write Stack Segment High Register (STACKSEGH) (Address = 0x001B) Bit(s) Value Description...
Page 72 /CS2 is active for accesses in this bank. /CS3 (internal memory) is active for accesses in this bank. When standalone operation is selected (by strapping a pin), this bit combination is forced for MB0CR only. Rabbit 5000 Microprocessor User’s Manual...
Page 73 MMU Expanded Code Register (MECR) (Address = 0x0018) Bit(s) Value Description Bank select address is A[19:18]. Bank select address is A[20:19]. Bank select address is A[21:20]. Bank select address is A[22:21]. Bank select address is A[23:22]. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used.
Page 74 Page-Mode 8-bit operation for /CS1. Normal 16-bit operation for /CS1. Page-Mode 16-bit operation for /CS1. Normal 8-bit operation for /CS0. Page-Mode 8-bit operation for /CS0. Normal 16-bit operation for /CS0. Page-Mode 16-bit operation for /CS0. Rabbit 5000 Microprocessor User’s Manual...
Page 75 Advanced Chip Select x Control Register (ACS0CR) (Address = 0x0410) (ACS1CR) (Address = 0x0411) (ACS2CR) (Address = 0x0412) Bit(s) Value Description Zero extra wait states for reads, writes, or first Page-Mode access. One extra wait state for reads, writes, or first Page-Mode read access. Two extra wait states for reads, writes, or first Page-Mode access.
Page 76 Write Protection Control Register (WPCR) (Address = 0x0440) Bit(s) Value Description These bits are reserved and should be written with zeros. Write protection in User Mode only. Write protection in System and User modes. Rabbit 5000 Microprocessor User’s Manual...
Page 77 Write-Protect x Register (WP0R) (Address = 0x0460) (WP1R) (Address = 0x0461) (WP2R) (Address = 0x0462) (WP3R) (Address = 0x0463) (WP4R) (Address = 0x0464) (WP5R) (Address = 0x0465) (WP6R) (Address = 0x0466) (WP7R) (Address = 0x0467) (WP8R) (Address = 0x0468) (WP9R) (Address = 0x0469) (WP10R) (Address = 0x046A)
Page 78 Enable 4 KB write protect for relative address 0x1000–0x1FFF in WP Segment x. Disable 4 KB write protect for relative address 0x0000–0x0FFF in WP Segment x. Enable 4 KB write protect for relative address 0x0000–0x0FFF in WP Segment x. Rabbit 5000 Microprocessor User’s Manual...
Page 79 Write-Protect Segment x High Register (WPSAHR) (Address = 0x0482) (WPSBHR) (Address = 0x0486) Bit(s) Value Description Disable 4 KB write protect for relative address 0xF000–0xFFFF in WP Segment x. Enable 4 KB write protect for relative address 0xF000–0xFFFF in WP Segment x. Disable 4 KB write protect for relative address 0xE000–0xEFFF in WP Segment x.
Page 80 (STKHLR) (Address = 0x0446) Bit(s) Value Description Upper limit for stack-limit checking. If a stack operation or stack-relative memory access is attempted at an address greater than {STKHLR, 0xEF}, a stack-limit violation interrupt is generated. Rabbit 5000 Microprocessor User’s Manual...
Page 81: Chapter 6. Interrupts 6.1 Overview
NTERRUPTS 6.1 Overview The Rabbit 5000 can operate at one of four priority levels, 0–3, with Priority 0 being the expected standard operating level. The current priority and up to three previous priority levels are kept in the processor’s 8-bit IP register, where bits 0–1 contain the current priority.
Page 82: Operation
Input Capture 0xB0 Timer B Stack Limit Violation 0xC0 Serial Port A Serial Port E 0xD0 Serial Port B Serial Port F 0xE0 Serial Port C Network Port B/C 0xF0 Serial Port D Timer C Rabbit 5000 Microprocessor User’s Manual...
Page 83 Table 6-2 shows the structure of the external interrupt vector table. Each interrupt vector falls on a 16-byte boundary inside the table. Table 6-2. External Interrupt Vector Table Structure Offset 0x0000+ 0x00 External Interrupt 0 0x10 External Interrupt 1 0x20 —...
Page 84 Serial Port C Tx: Write to SCDR, SCAR, SCLR or dummy write to SCSR. Rx: Read from SDDR or SDAR. Lowest Serial Port D Tx: Write to SDDR, SDAR, SDLR or dummy write to SDSR. Rabbit 5000 Microprocessor User’s Manual...
Page 85: Chapter 7. External Interrupts
The signal on the external interrupt pin must be present for at least three peripheral clock cycles to be detected. In addition, the Rabbit 5000 has a minimum latency of 11 clocks to respond to an interrupt, so the minimum external interrupt response time is three periph- eral clock cycles plus 11 processor clock cycles.
Page 86: Registers
7.3.1 I/O Pins The external interrupts can be enabled on pins PD0, PD1, PE0, PE1, PE4, and PE5. Each pin is associated with a particular interrupt vector as shown in Table 7-1 below. Table 7-1. Rabbit 5000 Interrupt Vectors Vector Register...
Page 87: Example Isr
7.4.1 Example ISR A sample interrupt handler is shown below. extInt_isr:: ; respond to external interrupt here ; interrupt is automatically cleared by interrupt acknowledge ipres Chapter 7 External Interrupts...
Page 88: Register Descriptions
Parallel Port E low nibble interrupt on both edges. This external interrupt is disabled. This external interrupt uses Interrupt Priority 1. This external interrupt uses Interrupt Priority 2. This external interrupt uses Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 89: Chapter 8 Parallel Port A
8. P ARALLEL 8.1 Overview Parallel Port A is a byte-wide port that can be used as an input or an output port. Parallel Port A is also used as the data bus for the slave port and external I/O bus. The Slave Port Control Register (SPCR) is used to configure how Parallel Port A is used.
Page 90: Dependencies
Parallel Port A is not available for general-purpose I/O while the slave port or the external I/O bus is selected. Selecting these options for Parallel Port A affects Parallel Port B because Parallel Port B is then used for address and control signals. Rabbit 5000 Microprocessor User’s Manual...
Page 91: Register Descriptions
8.4 Register Descriptions Parallel Port A Data Register (PADR) (Address = 0x0030) Bit(s) Value Description Read The current state of Parallel Port A pins PA7–PA0 is reported. The Parallel Port A buffer is written with this value for transfer to the Parallel Write Port A output register on the next rising edge of the peripheral clock.
Page 92 Rabbit 5000 Microprocessor User’s Manual...
Page 93: Overview
9. P ARALLEL 9.1 Overview Parallel Port B is a byte-wide port with each bit programmable for direction. The Parallel Port B pins are also used to access other peripherals on the chip—the slave port, the auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B.
Page 94: Block Diagram
All outputs on Parallel Port B are clocked by the peripheral clock (perclk). 9.2.3 Other Registers Register Function Sets the Parallel Port B function for some pins if the SPCR slave port or external I/O bus is enabled. Rabbit 5000 Microprocessor User’s Manual...
Page 95: Interrupts
9.2.4 Interrupts There are no interrupts associated with Parallel Port B, except when the slave port is being used. 9.3 Operation The following steps must be taken before using Parallel Port B. 1. Select the desired input/output direction for each pin via PBDDR. Note that this setting is superseded for some pins if the slave port or external I/O bus is enabled in SPCR or if the clocked serial mode is enabled for Serial Ports A or B.
Page 96 Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus. Slave port interrupts are disabled. Slave port interrupts use Interrupt Priority 1. Slave port interrupts use Interrupt Priority 2. Slave port interrupts use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 97: Overview
10. P ARALLEL 10.1 Overview Parallel Port C is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port C Data Reg- ister (PCDR). All the Parallel Port C pins have alternate output functions, and most of them can be used as inputs to various on-chip peripherals.
Page 98: Block Diagram
Port C Data Direction Register PCDDR 0x0051 01010101 Port C Alternate Low Register PCALR 0x0052 00000000 Port C Alternate High Register PCAHR 0x0053 00000000 Port C Drive Control Register PCDCR 0x0054 00000000 Port C Function Register PCFR 0x0055 00000000 Rabbit 5000 Microprocessor User’s Manual...
Page 99: Dependencies
10.2 Dependencies 10.2.1 I/O Pins Parallel Port C uses pins PC0 through PC7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial ports A–F; as clocks for Serial Ports C–F; as external I/O strobes; or as outputs for the PWM and Timer C periph- erals.
Page 100: Register Descriptions
Parallel Port C bit 0 alternate output 0 (TXD). Parallel Port C bit 0 alternate output 1 (I0). Parallel Port C bit 0 alternate output 2 (TIMER C0). Parallel Port C bit 0 alternate output 3 (TCLKF). Rabbit 5000 Microprocessor User’s Manual...
Page 101 Parallel Port C Alternate High Register (PCAHR) (Address = 0x0053) Bit(s) Value Description Parallel Port C bit 7 alternate output 0 (TXA). Parallel Port C bit 7 alternate output 1 (I7). Parallel Port C bit 7 alternate output 2 (PWM3). Parallel Port C bit 7 alternate output 3 (SCLKC).
Page 102 Clocked serial mode with external clock. Clocked serial mode with internal clock. The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 103 Input Capture Source x Register (ICS1R) (Address = 0x0059) (ICS2R) (Address = 0x005D) Bit(s) Value Description Parallel Port C used for Start condition input. Parallel Port D used for Start condition input. Parallel Port E used for Start condition input. This bit combination is reserved and should not be used.
Page 104 Rabbit 5000 Microprocessor User’s Manual...
Page 105: Overview
11. P ARALLEL 11.1 Overview Parallel Port D is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port D Data Register (PDDR). All of the Parallel Port D pins have alternate output functions, and all of them can be used as inputs to various on-chip peripherals.
Page 106 Table 11-2. Parallel Port D Pin Alternate Input Functions Input Serial Serial External Quad Pin Name Capture Ports A–D Ports E–F Interrupts Decode × — — — — — — — — — × RCLKE — — — — — TCLKE —...
Page 107: Block Diagram
11.1.1 Block Diagram Chapter 11 Parallel Port D...
Page 108: Registers
11.1.2 Registers Register Name Mnemonic I/O Address Reset Port D Data Register PDDR 0x0060 xxxxxxxx Port D Alternate Low Register PDALR 0x0062 00000000 Port D Alternate High Register PDAHR 0x0063 00000000 Port D Control Register PDCR 0x0064 xx00xx00 Port D Function Register PDFR 0x0065 xxxxxxxx...
Page 109: Dependencies
11.2 Dependencies 11.2.1 I/O Pins Parallel Port D uses pins PD0 through PD7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial Ports A, B, E, and F; as clocks for Serial Ports C–F;...
Page 110: Operation
11.3 Operation The following steps must be taken before using Parallel Port D. 1. Select the desired input/output direction for each pin via PDDDR. 2. Select high/low or open-drain functionality for outputs via PDDCR. 3. If an alternative peripheral output function is desired for a pin, select it via PDALR or PDAHR and then enable it via PDFR.
Page 111: Register Descriptions
11.4 Register Descriptions Parallel Port D Data Register (PDDR) (Address = 0x0060) Bit(s) Value Description Read The current state of Parallel Port D pins PD7–PD0 is reported. The Parallel Port D buffer is written with this value for transfer to the Parallel Write Port D output register on the next rising edge of the port transfer clock.
Page 112 Parallel Port D Alternate High Register (PDAHR) (Address = 0x0063) Bit(s) Value Description Parallel Port D bit 7 alternate output 0 (IA7). Parallel Port D bit 7 alternate output 1 (I7). Parallel Port D bit 7 alternate output 2 (PWM3). Parallel Port D bit 7 alternate output 3 (SCLKC).
Page 113 Parallel Port D Function Register (PDFR) (Address = 0x0065) Bit(s) Value Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 11-1. Parallel Port D Drive Control Register (PDDCR) (Address = 0x0066) Bit(s) Value Description...
Page 114 Parallel Port D Bit 2 Register (PDB2R) (Address = 0x006A) Bit(s) Value Description 7:3,1:0 These bits are ignored. The port buffer (bit 2) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the port transfer clock Parallel Port D Bit 3 Register (PDB3R)
Page 115 Parallel Port D Bit 6 Register (PDB6R) (Address = 0x006E) Bit(s) Value Description 7,5:0 These bits are ignored. The port buffer (bit 6) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the port transfer clock Parallel Port D Bit 7 Register (PDB7R)
Page 116 Serial Port x Control Register (SACR) (Address = 0x00C4) (SBCR) (Address = 0x00D4) (SCCR) (Address = 0x00E4) (SDCR) (Address = 0x00F4) Bit(s) Value Description No operation. These bits are ignored in the asynchronous mode. In the clocked serial mode, start a byte-receive operation. In the clocked serial mode, start a byte-transmit operation.
Page 117 Input Capture Source x Register (ICS1R) (Address = 0x0059) (ICS2R) (Address = 0x005D) Bit(s) Value Description Parallel Port C used for Start condition input. Parallel Port D used for Start condition input. Parallel Port E used for Start condition input. This bit combination is reserved and should not be used.
Page 118 Quad Decode Control Register (QDCR) (Address = 0x0091) Bit(s) Value Description Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. Quadrature Decoder 2 inputs from Parallel Port D bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2.
Page 119 Interrupt x Control Register (I0CR) (Address = 0x0098) (I1CR) (Address = 0x0099) Bit(s) Value Description Parallel Port D low nibble interrupt disabled. Parallel Port D low nibble interrupt on falling edge. Parallel Port D low nibble interrupt on rising edge. Parallel Port D low nibble interrupt on both edges.
Page 120 DMA Master Request 0 Control Register (DMR0CR) (Address = 0x0106) Bit(s) Value Description External DMA Request 0 disabled. External DMA Request 0 enabled from Parallel Port D2. External DMA Request 0 enabled from Parallel Port E2. External DMA Request 0 enabled from Parallel Port E6. This bit is reserved and should be written with zero.
Page 121 DMA Master Request 1 Control Register (DMR1CR) (Address = 0x0107) Bit(s) Value Description External DMA Request 1 disabled. External DMA Request 1 enabled from Parallel Port D3. External DMA Request 1 enabled from Parallel Port E3. External DMA Request 1 enabled from Parallel Port E7. This bit is reserved and should be written with zero.
Page 122 Rabbit 4000 Microprocessor User’s Manual...
Page 123: Overview
12. P ARALLEL 12.1 Overview Parallel Port E is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port E Data Register (PEDR). All of the Parallel Port E pins have alternate output functions, and all of them can be used as inputs to various on-chip peripherals.
Page 124 — INT1 — × — — TCLKE — INT0 — × × DREQ1 — QRD2A × — SCLKC — DREQ0 — QRD2B × × RCLKF — INT1 QRD1A × — SCLKD TCLKF — INT0 QRD1B Rabbit 5000 Microprocessor User’s Manual...
Page 125: Block Diagram
12.1.1 Block Diagram Chapter 12 Parallel Port E...
Page 126: Registers
All outputs on Parallel Port E are clocked by the peripheral clock unless changed in PECR, where the option of updating the Parallel Port E pins can be synchronized to the output of Timer A1, Timer B1, or Timer B2. Rabbit 5000 Microprocessor User’s Manual...
Page 127: Other Registers
12.2.3 Other Registers Register Function SACR, SBCR, SCCR, Select a Parallel Port E pin as serial data (and SDCR, SECR, SFCR optional clock) input. Select a Parallel Port E pin as a start/stop condition ICS1R, ICS2R for Input Capture input. Select a Parallel Port E pin as a Quadrature Decoder QDCR input.
Page 128: Register Descriptions
Parallel Port E bit 0 alternate output 0 (I0). Parallel Port E bit 0 alternate output 1 (A20). Parallel Port E bit 0 alternate output 2 (TIMER C0). Parallel Port E bit 0 alternate output 3 (TCLKF). Rabbit 5000 Microprocessor User’s Manual...
Page 129 Parallel Port E Alternate High Register (PEAHR) (Address = 0x0073) Bit(s) Value Description Parallel Port E bit 7 alternate output 0 (I7). Parallel Port E bit 7 alternate output 1 (no functionality). Parallel Port E bit 7 alternate output 2 (PWM3). Parallel Port E bit 7 alternate output 3 (SCLKC).
Page 130 These bits are ignored. The port buffer (bit 1) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock. Rabbit 5000 Microprocessor User’s Manual...
Page 131 Parallel Port E Bit 2 Register (PEB2R) (Address = 0x007A) Bit(s) Value Description 7:3,1:0 These bits are ignored. The port buffer (bit 2) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock.
Page 132 These bits are ignored. The port buffer (bit 7) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock. Rabbit 5000 Microprocessor User’s Manual...
Page 133 Serial Port x Control Register (SACR) (Address = 0x00C4) (SBCR) (Address = 0x00D4) (SCCR) (Address = 0x00E4) (SDCR) (Address = 0x00F4) Bit(s) Value Description No operation. These bits are ignored in the asynchronous mode. In the clocked serial mode, start a byte-receive operation. In the clocked serial mode, start a byte-transmit operation.
Page 134 This bit combination is reserved and should not be used. Use port bit 1 for Stop condition input. Use port bit 3 for Stop condition input. Use port bit 5 for Stop condition input. Use port bit 7 for Stop condition input. Rabbit 5000 Microprocessor User’s Manual...
Page 135 Quad Decode Control Register (QDCR) (Address = 0x0091) Bit(s) Value Description Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. Quadrature Decoder 2 inputs from Parallel Port D bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2.
Page 136 Parallel Port E low nibble interrupt on both edges. This external interrupt is disabled. This external interrupt uses Interrupt Priority 1. This external interrupt uses Interrupt Priority 2. This external interrupt uses Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 137 DMA Master Request 0 Control Register (DMR0CR) (Address = 0x0106) Bit(s) Value Description External DMA Request 0 disabled. External DMA Request 0 enabled from Parallel Port D2. External DMA Request 0 enabled from Parallel Port E2. External DMA Request 0 enabled from Parallel Port E6. This bit is reserved and should be written with zero.
Page 138 External DMA Request 1 supplied to DMA Channel 4. External DMA Request 1 supplied to DMA Channel 5. External DMA Request 1 supplied to DMA Channel 6. External DMA Request 1 supplied to DMA Channel 7. Rabbit 5000 Microprocessor User’s Manual...
Page 139 Slave Port Control Register (SPCR) (Address = 0x0024) Bit(s) Value Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. Read These bits report the state of the SMODE pins. Write These bits are ignored and should be written with zero. Disable the slave port.
Page 140 Use Parallel Port E bit 4 for I/O handshake. Use Parallel Port E bit 5 for I/O handshake. Use Parallel Port E bit 6 for I/O handshake. Use Parallel Port E bit 7 for I/O handshake. Rabbit 5000 Microprocessor User’s Manual...
Page 141 I/O Handshake Select Register (IHSR) (Address = 0x0029) Bit(s) Value Description Disable I/O handshake for I/O Bank 7. Enable I/O handshake for I/O Bank 7. Disable I/O handshake for I/O Bank 6. Enable I/O handshake for I/O Bank 6. Disable I/O handshake for I/O Bank 5. Enable I/O handshake for I/O Bank 5.
Page 142 Rabbit 5000 Microprocessor User’s Manual...
Page 143: Overview
13. P ARALLEL 13.1 Overview Parallel Port H is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port H Data Register (PHDR). All of the Parallel Port H pins have alternate output functions. When used as outputs, the Parallel Port H bits are buffered, with the data written to PHDR transferred to the output pins.
Page 144: Block Diagram
Port H Alternate Low Register PHALR 0x0032 00000000 Port H Alternate High Register PHAHR 0x0033 00000000 Port H Function Register PHFR 0x0035 00000000 Port H Drive Control Register PHDCR 0x0036 00000000 Port H Data Direction Register PHDDR 0x0037 00000000 Rabbit 5000 Microprocessor User’s Manual...
Page 145: Dependencies
13.2 Dependencies 13.2.1 I/O Pins Parallel Port H uses pins PH0 through PH7. These pins can be used individually as data inputs or outputs; as the serial port transmit for Serial Ports E and F; as the clock transmit (internal clock mode) for Serial Ports C–F; as external I/O strobes; or as outputs for the PWM and Timer C peripherals.
Page 146: Register Descriptions
This value is reserved and must not be used. Parallel Port H bit 0 alternate output 1 (I0). Parallel Port H bit 0 alternate output 2 (TIMER C0). Parallel Port H bit 0 alternate output 3 (TCLKF). Rabbit 5000 Microprocessor User’s Manual...
Page 147 Parallel Port H Alternate High Register (PHAHR) (Address = 0x0033) Bit(s) Value Description This value is reserved and must not be used. Parallel Port H bit 7 alternate output 1 (I7). Parallel Port H bit 7 alternate output 2 (PWM3). Parallel Port H bit 7 alternate output 3 (SCLKC).
Page 148 Page-Mode 8-bit operation for /CS1. Normal 16-bit operation for /CS1. Page-Mode 16-bit operation for /CS1. Normal 8-bit operation for /CS0. Page-Mode 8-bit operation for /CS0. Normal 16-bit operation for /CS0. Page-Mode 16-bit operation for /CS0. Rabbit 5000 Microprocessor User’s Manual...
Page 149: Overview
Timers A2–A7 can be used to generate baud rates for Serial Ports A–F, or they can be used as general-purpose timers if the dedicated timers on the Rabbit 5000 serial ports are used. The three remaining timers (A8–A10) serve as prescalers for the input capture, PWM, and quadrature decoder peripherals respectively.
Page 150 After these bits are cleared, they cannot cause an interrupt. The proper rule to follow is for the interrupt routine to handle all bits that it sees set. Rabbit 5000 Microprocessor User’s Manual...
Page 151: Block Diagram
14.1.1 Block Diagram Chapter 14 Timer A...
Page 152: Registers
The timers in Timer A can be clocked by either perclk or perclk/2, as selected in TAPR. In addition, Timers A2–A7 can be clocked by the output of Timer A1 by selecting that option in TACSR. 14.2.3 Other Registers Register Function GCSR Select peripheral clock mode. Rabbit 5000 Microprocessor User’s Manual...
Page 153: Interrupts
14.2.4 Interrupts A Timer A interrupt can be generated whenever Timers A1–A7 decrement to zero by enabling the appropriate bit in TACSR. The interrupt request is cleared when TACSR is read. The Timer A interrupt vector is in the IIR at offset 0x0A0. It can be set as priority 1, 2, or 3 in TACR.
Page 154: Register Descriptions
These bits are reserved and should be written with zero. The main clock for Timer A is the peripheral clock (perclk). The main clock for Timer A is the peripheral clock divided by two (perclk/2). Rabbit 5000 Microprocessor User’s Manual...
Page 155 Timer A Control Register (TACR) (Address = 0x00A4) Bit(s) Value Description Timer A7 clocked by the main Timer A clock. Timer A7 clocked by the output of Timer A1. Timer A6 clocked by the main Timer A clock. Timer A6 clocked by the output of Timer A1. Timer A5 clocked by the main Timer A clock.
Page 156 Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Rabbit 5000 Microprocessor User’s Manual...
Page 157: Overview
15. T IMER 15.1 Overview The Timer B peripheral consists of a ten-bit free running up-counter, two match registers, and two step registers. Timer B is driven by perclk/2, by perclk/16, or by the output of Timer A1. Timer B generates an output pulse whenever the counter reaches the match value.
Page 158: Registers
Select peripheral clock mode. 15.2.4 Interrupts A Timer B interrupt can be generated whenever the counter equals one of the match registers by enabling the appropriate bit in TBCSR. The interrupt request is cleared when TBCSR is read. Rabbit 5000 Microprocessor User’s Manual...
Page 159: Operation
15.3 Operation The following steps explain how to set up a Timer B countdown timer. 1. Select perclk/2, perclk/16, or countdown Timer A1 in TBCR. 2. Use TBCR to select whether countdown Timers B1–B2 operate normally with the match registers or whether they use the step registers to calculate match values. 3.
Page 160: Register Descriptions
Timer B clocked by the peripheral clock divided by 16. Timer B interrupts are disabled. Timer B interrupt use Interrupt Priority 1. Timer B interrupt use Interrupt Priority 2. Timer B interrupt use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 161 Timer B Count MSB x Register (TBM1R) (Address = 0x00B2) (TBM2R) (Address = 0x00B4) Bit(s) Value Description Two MSBs of the compare value for the Timer B comparator. This compare value will be loaded into the actual comparator when the current compare detects a match.
Page 162 Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Rabbit 5000 Microprocessor User’s Manual...
Page 163: Overview
16. T IMER 16.1 Overview The Timer C peripheral is a 16-bit up-counter clocked by the peripheral clock divided by 2, by the peripheral clock divided by 16, or by the output of countdown Timer A1. The coun- ter counts from zero to the limit programmed into the Timer C divider registers and then restarts at zero, so the overall cycle count is the value in the divider registers plus one.
Page 164: Block Diagram
16.1.1 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 165: Registers
16.1.2 Registers Register Name Mnemonic I/O Address Reset Timer C Control/Status Register TCCSR 0x0500 xxxx0000 Timer C Control Register TCCR 0x0501 xx000000 Timer C Divider Low Register TCDLR 0x0502 00000000 Timer C Divider High Register TCDHR 0x0503 00000000 Timer C Set 0 Low Register TCS0LR 0x0508 xxxxxxxx...
Page 166: Dependencies
Alternate port output selection PEFR, PEALR PHFR, PHALR 16.2.4 Interrupts A Timer C interrupt is enabled in TCCR, and will occur whenever the count limit value is reached. The interrupt request is cleared when TCCSR is read. Rabbit 5000 Microprocessor User’s Manual...
Page 167: Operation
16.3 Operation The following steps explain how to set up a Timer C timer. 1. Select perclk/2, perclk/16, or countdown Timer A1 in TCCR. 2. Load the desired upper limit for the counter into TCDLR and TCDHR. The overall clock count per Timer C cycle will be the value loaded into the divider registers plus one.
Page 168: Register Descriptions
The eight LSBs of the divider limit value for Timer C are stored. Timer C Divider High Register (TCDHR) (Address = 0x0503) Bit(s) Value Description The eight MSBs of the divider limit value for Timer C are stored. Rabbit 5000 Microprocessor User’s Manual...
Page 169 Timer C Set x Low Register (TCS0LR) (Address = 0x0508) (TCS1LR) (Address = 0x050C) (TCS2LR) (Address = 0x0518) (TCS3LR) (Address = 0x051C) Bit(s) Value Description Eight LSBs of the match value to set Timer C Output x. Timer C Set x High Register (TCS0HR) (Address = 0x0509) (TCS1HR)
Page 170 Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Rabbit 5000 Microprocessor User’s Manual...
Page 171: Overview
17. S A – D ERIAL ORTS 17.1 Overview Serial Ports A, B, C, and D are identical, except for the source of the data clock and the transmit, receive, and clock pins. In addition to being used as a regular serial port, Serial Port A can be used to bootstrap the processor.
Page 172 When Serial Port A is used in the asynchronous bootstrap mode, the 32 kHz clock is used to generate the expected 2400 bps data rate. An external clock must be supplied for the clocked serial bootstrap mode. Rabbit 5000 Microprocessor User’s Manual...
Page 173: Block Diagram
The behavior of the serial port during a break (line held low) is configurable; character assembly can continue during the break condition to allow for timing the break, or charac- ter assembly can be inhibited to reduce the interrupt overhead. 17.1.1 Block Diagram Chapter 17 Serial Ports A –...
Page 174: Registers
0xx00000 Serial Port D Control Register SDCR 0x00F4 xx000000 Serial Port D Extended Register SDER 0x00F5 00000000 Serial Port D Divider Low Register SDDLR 0x00F6 xxxxxxxx Serial Port D Divider High Register SDDHR 0x00F7 0xxxxxxx Rabbit 5000 Microprocessor User’s Manual...
Page 175: Dependencies
17.2 Dependencies 17.2.1 I/O Pins Serial Port A can transmit on parallel port pins PC7, PC6, or PD6, and can receive on pins PC7, PD7, or PE7. If the clocked serial mode is enabled, the serial clock is either transmit- ted or received on PB1.
Page 176: Other Registers
• Serial Port C at offset 0x0E0 • Serial Port D at offset 0x0F0 Each of them can be set as Priority 1, 2, or 3 in SxCR, where x is A – D for the four serial ports. Rabbit 5000 Microprocessor User’s Manual...
Page 177: Operation
17.3 Operation TIP: Remember to set up the serial port bits before commanding the serial port to send or receive any data. 17.3.1 Asynchronous Mode The following steps explain how to set up Serial Ports A – D for asynchronous operation. The serial ports can be used by polling the status byte, but their performance will be better with an interrupt.
Page 178: Clocked Serial Mode
The following steps explain how to set up Serial Ports A – D for the clocked serial mode. When the internal clock is selected, the Rabbit 5000 is in control of all transmit and receive operations. When an external clock is selected the other device controls all trans- mit and receive operation.
Page 179 A sample clocked serial interrupt handler is shown below for Serial Port B. clocked_serb_isr:: push af ; save used registers ioi ld a, (SBSR) ; get status bit 7,a ; check if byte ready in RX buffer push af ; save status for next check z, check_for_tx rx_ready: ioi ld a, (SBDR)
Page 180: Register Descriptions
(Address = 0x00E2) (SDLR) (Address = 0x00F2) Bit(s) Value Description Read Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a “one” address bit, Write for transmission. Rabbit 5000 Microprocessor User’s Manual...
Page 181 Serial Port x Status Register (SASR) (Address = 0x00C3) (Asynchronous Mode Only) (SBSR) (Address = 0x00D3) (SCSR) (Address = 0x00E3) (SDSR) (Address = 0x00F3) Bit(s) Value Description The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set.
Page 182 The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. These bits are always zero in the clocked serial mode. Rabbit 5000 Microprocessor User’s Manual...
Page 183 Serial Port x Control Register (SACR) (Address = 0x00C4) (SBCR) (Address = 0x00D4) (SCCR) (Address = 0x00E4) (SDCR) (Address = 0x00F4) Bit(s) Value Description No operation. These bits are ignored in the asynchronous mode. In the clocked serial mode, start a byte-receive operation. In the clocked serial mode, start a byte-transmit operation.
Page 184 Continue character assembly during break to allow timing the break condition. Inhibit character assembly during break. One character (all zeros, with framing error) at start and one character (garbage) at completion. This bit is ignored in the asynchronous mode. Rabbit 5000 Microprocessor User’s Manual...
Page 185 Serial Port x Extended Register (SAER) (Address = 0x00C5) (Clocked Serial Mode Only) (SBER) (Address = 0x00D5) (SCER) (Address = 0x00E5) (SDER) (Address = 0x00F5) Bit(s) Value Description Normal clocked serial operation. Timer-synchronized clocked serial operation. Timer-synchronized clocked serial uses Timer B1. Timer-synchronized clocked serial uses Timer B2.
Page 186 Enable the serial port divider, and use its output to clock the serial port. The serial port divider counts modulo n + 1 and is clocked by the peripheral clock. Seven MSBs of the divider that generates the serial clock for this channel. Rabbit 5000 Microprocessor User’s Manual...
Page 187: Overview
18. S E – F ERIAL ORTS 18.1 Overview Serial Ports E and F are identical to each other, and their asynchronous operation is identi- cal to that of Serial Ports A – D except for the source of the data clock, the buffer sizes, and the transmit, receive, and clock pins.
Page 188: Block Diagram
For more on the clock synchro- nization and data encoding, see Section 18.3.3. 18.1.1 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 189: Registers
18.1.2 Registers Register Name Mnemonic I/O Address Reset Serial Port E Data Register SEDR 0x00C8 xxxxxxxx Serial Port E Address Register SEAR 0x00C9 xxxxxxxx Serial Port E Long Stop Register SELR 0x00CA xxxxxxxx Serial Port E Status Register SESR 0x00CB 0xx00000 Serial Port E Control Register SECR...
Page 190: Dependencies
18.2.3 Other Registers Register Function TAT2R Time constant for Serial Port E TAT3R Time constant for Serial Port F PCFR, PCAHR, PCALR PDFR, PDAHR, PDALR Alternate port output selection PEFR, PEAHR, PEALR PHFR, PHAHR, PHALR Rabbit 5000 Microprocessor User’s Manual...
Page 191: Interrupts
18.2.4 Interrupts In the asynchronous mode, a serial port interrupt can be generated whenever one of the following occurs. • A byte is available in the receive buffer. • A byte is moved from the transmit buffer to the transmitter. •...
Page 192: Operation
(i.e., it is not addressed to this device), writing a 01 to bits 6–7 of SxCR will force the receiver back into the flag search mode. Rabbit 5000 Microprocessor User’s Manual...
Page 193: More On Clock Synchronization And Data Encoding
A sample HDLC interrupt handler is shown below for Serial Port E. hdlc_sere_isr:: push af ioi ld a, (SESR) ; get status bit 7,a ; check if byte ready in RX buffer push af ; save status for next check z, check_for_tx rx_ready: ;...
Page 194 DPLL-tracked bit-cell boundaries, so the count is shortened by either one or two counts. If the transition occurs later than expected, it means that the bit-cell boundaries are late with Rabbit 5000 Microprocessor User’s Manual...
Page 195 respect to the DPLL-tracked bit-cell boundaries, so the count is lengthened by either one or two counts. The decision to adjust by one or by two depends on how far off the DPLL- tracked bit cell boundaries are. This tracking allows for minor differences in the transmit and receive clock frequencies.
Page 196 Decoding biphase-level data requires that the data be sampled at either the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to sample the data. Rabbit 5000 Microprocessor User’s Manual...
Page 197: Register Descriptions
Biphase-mark encoding and biphase-space encoding are identical as far as the DPLL is concerned, and are similar to biphase-level encoding. The primary difference is the place- ment of the clock and data transitions. With these encodings the clock transitions are at the bit-cell boundary, the data transitions are at the center of the bit cell, and the DPLL opera- tion is adjusted accordingly.
Page 198 The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. These bits are always zero in the asynchronous mode. Rabbit 5000 Microprocessor User’s Manual...
Page 199 Serial Port x Status Register (SESR) (Address = 0x00CB) (HDLC Mode Only) (SFSR) (Address = 0x00DB) Bit(s) Value Description The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set.
Page 200 If necessary, the receiver and transmitter clocks can be output via parallel port pins. The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 201 Serial Port x Extended Register (SEER) (Address = 0x00CD) (Asynchronous Mode Only) (SFER) (Address = 0x00DD Bit(s) Value Description Disable parity generation and checking. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used.
Page 202 Enable the serial port divider, and use its output to clock the serial port. The serial port divider counts modulo n + 1 and is clocked by the peripheral clock. Seven MSBs of the divider that generates the serial clock for this channel. Rabbit 5000 Microprocessor User’s Manual...
Page 203: Overview
19. S LAVE 19.1 Overview The slave port is a parallel communication port that can be used to communicate with an external master device. The slave port consists of three data input and data output regis- ters, and a status register. The data input registers are written by the master (the external device) and are read by the processor.
Page 204: Block Diagram
Slave Port Data 0 Register SPD0R 0x0020 xxxxxxxx Slave Port Data 1 Register SPD1R 0x0021 xxxxxxxx Slave Port Data 2 Register SPD2R 0x0022 xxxxxxxx Slave Port Status Register SPSR 0x0023 00000000 Slave Port Control Register SPCR 0x0024 0xx00000 Rabbit 5000 Microprocessor User’s Manual...
Page 205: Dependencies
19.2 Dependencies 19.2.1 I/O Pins When the slave port is enabled by writing to SPCR, the following pins are enabled for slave port mode. Note that enabling the slave port mode will override any general-purpose I/O or external I/O bus settings for these pins; when the slave port is enabled they will per- form slave port functionality.
Page 206: Operation
19.3 Operation Figure 19-1 shows a typical slave port connection between a Rabbit processor as the master and two slaves. Figure 19-1. Master/Slave Port Connections Rabbit 5000 Microprocessor User’s Manual...
Page 207: Master Setup
These connections are summarized in Table 19-3. Table 19-3. Typical Slave Port Connections Master Slave #1 Slave #2 Data Bus D0–D7 SD0–SD7 PA0–PA7 SD0–SD7 PA0–PA7 Address Bus A0–A1 SA0–SA1 PB4–PB5 SA0–SA1 PB4–PB5 I/O Read Strobe /IORD /SRD /SRD I/O Write Strobe /IOWR /SWR /SWR...
Page 208: Master/Slave Communication
(SPD1R), a ld a, (to_mas_d0) ioi ld (SPD0R), a ; this write asserts /SLVATTN ; the interrupt request is cleared by any read/write of the registers pop af ; restore used registers ipres Rabbit 5000 Microprocessor User’s Manual...
Page 209: Other Configurations
19.3.7 Other Configurations There are other slave port configurations possible: • The master could use the external I/O bus instead of the memory bus. • All devices could poll the slave port status register to determine when data is present instead of relying on interrupts.
Page 210: Timing Diagrams
19.3.8 Timing Diagrams Figure 19-2 shows the sequence of events when the master reads/writes the slave port registers. Slave Port Read Cycle Slave Port Write Cycle Figure 19-2. Slave Port R/W Timing Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 211 The following table explains the parameters used in Figure 19-2. Minimum Maximum Symbol Parameter (ns) (ns) Tsu(SCS) /SCS Setup Time — Th(SCS) /SCS Hold Time — Tsu(SA) SA Setup Time — Th(SA) SA Hold Time — Tw(SRD) /SRD Low Pulse Width —...
Page 212: Register Descriptions
Slave port write byte 2 is full. Slave port write byte 1 is empty. Slave port write byte 1 is full. Slave port write byte 0 is empty. Slave port write byte 0 is full. Rabbit 5000 Microprocessor User’s Manual...
Page 213 Slave Port Control Register (SPCR) (Address = 0x0024) Bit(s) Value Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. Read These bits report the state of the SMODE pins. Write These bits are ignored and should be written with zero. Disable the slave port.
Page 214 Rabbit 5000 Microprocessor User’s Manual...
Page 215: Overview
NALOG OMPONENTS 20.1 Overview The Rabbit 5000 has a 10-bit single-channel A/D converter, a 10-bit two-channel differential-input A/D converter, and a 10-bit two-channel differential-output D/A converter for 802.11 Wi-Fi operation. These analog features are available for customer use when Wi-Fi is not being used. Table 20-1 summarizes the analog features.
Page 216 2% of full scale ± I to Q Offset Mismatch 1% of full scale ± 5% of full scale Gain Error ± I to Q Gain Mismatch 1% of full scale Channel Isolation 60 dB typ. Rabbit 5000 Microprocessor User’s Manual...
Page 217 Table 20-2. Analog Component Specifications (continued) Analog Component Feature Specification Resolution 10 bits Input Range 0 V to 3.3 V Operating Current Active 35 µA @ 1.8 V, 62 µA @ 3.3 V Standby < 1 µA @ 1.8 V, 3.3 V Transition Time 2 (slow A/D converter) Standby to active...
Page 218: Block Diagram
20.2 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 219: Registers
20.2.1 Registers Register Name Mnemonic I/O Address Reset Analog Component 0 I LSB Register A0ILR 0x0800 xxxxxxxx Analog Component 0 I MSB Register A0IMR 0x0801 xxxxxxxx Analog Component 0 Q LSB Register A0QLR 0x0802 xxxxxxxx Analog Component 0 Q MSB Register A0QMR 0x0803 xxxxxxxx...
Page 220: Operation
4. For faster update, an 8-bit value can be obtained by only reading A2MR. 5. To reduce power consumption, the slow A/D converter can be put into a sleep mode by writing to A2CR. Rabbit 5000 Microprocessor User’s Manual...
Page 221: Sample Circuits
20.5 Sample Circuits Sample circuits are shown below for the analog components. Since each analog compo- nent has dedicated power and ground, be sure to allow enough filtering for each block as shown — a range of ferrite beads may be used — we obtained good results with ferrite beads rated at 120 ...
Page 222 Ferrite Bead ANALOG INTPUT SLOW Figure 20-3. Sample Slow A/D Converter Circuit Rabbit 5000 Microprocessor User’s Manual...
Page 223: Register Descriptions
20.6 Register Descriptions Analog Component 0 I LSB Register (A0ILR) (Address = 0x0800) Analog Component 0 Q LSB Register (A0QLR) (Address = 0x0802) Bit(s) Value Description The current value of the two least-significant bits of the fast A/D converter are Read returned.
Page 224 D/A converter until the corresponding MSB register is written to guarantee that the full 10 bits are valid. Read These bits always return zeros when read. These bits are ignored and will always return zeros when read. Rabbit 5000 Microprocessor User’s Manual...
Page 225 Analog Component 1 I MSB Register (A1IMR) (Address = 0x0811) Analog Component 1 Q MSB Register (A1QMR) (Address = 0x0813) Bit(s) Value Description The eight most-significant bits for the fast D/A converter are stored. Writing Write these bits transfers the entire 10 bits to the fast D/A converter. Read These bits always return zeros when read.
Page 226 Analog Component 2 MSB Register (A2MR) (Address = 0x0821) Bit(s) Value Description The current value of the eight most-significant bits of the slow A/D converter are Read returned. Write Writes to this register are ignored. Rabbit 5000 Microprocessor User’s Manual...
Page 227 Analog Component 2 Control Register (A2CR) (Address = 0x0824) Bit(s) Value Description Use peripheral clock as slow A/D converter clock source. Use Parallel Port PD6 as slow A/D converter clock source. Clock divided by 2. Clock divided by 4. Clock divided by 8. Clock divided by 16.
Page 228 Rabbit 5000 Microprocessor User’s Manual...
Page 229: Overview
HANNELS 21.1 Overview There are eight independent DMA channels on the Rabbit 5000. All eight channels are identical, and are capable of transferring data to or from memory, external I/O, or internal I/O. The priority between the channels can be either fixed or rotating, and the DMA use of the bus can be limited to guarantee interrupt latency or CPU throughput.
Page 230 However, this function is not available in the case where the buffer contains only one byte of data. If this case should occur, the buffer descriptor must contain the special destination address. Rabbit 5000 Microprocessor User’s Manual...
Page 231 Normally all DMA transfers are flow-through, meaning that the DMA does separate read and write transactions to transfer the data. However, the Rabbit 5000 DMA also contains dedicated buses to support fly-by transactions to and from certain internal I/O addresses.
Page 232: Block Diagram
21.1.1 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 233: Registers
21.1.2 Registers Register Name Mnemonic I/O Address Reset DMA Master Control/Status Register DMCSR 0x0100 00000000 DMA Master Auto-Load Register DMALR 0x0101 00000000 DMA Master Halt Register DMHR 0x0102 00000000 DMA y Buffer Complete Register DyBCR 0x01y3 00000000 DMA Master Control Register DMCR 0x0104 00000000...
Page 234: Dependencies
The DMA interrupt vectors are in the EIR starting at offset 0x080 for DMA Channel 0 and ending at offset 0x0F0 for DMA Channel 7. They can be set as Priority 1, 2, or 3. Rabbit 5000 Microprocessor User’s Manual...
Page 235: Operation
21.3 Operation It is possible to set up and start a DMA operation by writing directly to all the relevant address, length, and control registers, but it is expected that the typical operation would be to create a buffer descriptor in memory, write the address of that descriptor to the initial address registers (DyIAnR), and use a write to DMALR to auto-load the values from memory into the registers and start the transfer.
Page 236: Handling Interrupts
21.3.3 DMA Priority with the Processor Since the Rabbit 5000 DMA uses the memory management unit to perform transfers, normal code execution cannot occur while the DMA is active. This includes handling interrupts, so it is important to limit the amount of time that the DMA can operate.
Page 237 Setting an interrupt priority to something greater than the DMA transfer priority will ensure that no DMA activity occurs during that interrupt handler. Note that when both an interrupt and a DMA transfer are pending, the DMA transfer will be selected for execution first (provided its priority is equal or greater than the current processor priority level).
Page 238: Dma Channel Priority
It is possible to control the priority between separate DMA channels. There are three channel-priority options in the Rabbit 5000. The first is fixed priority after every byte where the priority of each channel is equal to its number, i.e., if both DMA Channels 3 and 4 have a pending transfer request, DMA Channel 4 will always be enabled first.
Page 239: Single Buffer
21.3.5.1 Single Buffer In the simplest mode, a single descriptor is set to halt and interrupt on completion. 21.3.5.2 Buffer Array In this mode, an array of 12-byte descriptors is set up adjacent in memory; only the last buffer is set to halt on completion. The last buffer is also typically set to interrupt on com- pletion, but other buffer descriptors in the array can also generate interrupts.
Page 240: Linked List
A linked list is similar to a buffer array, except that 16-byte descriptors are used and the descriptors are not necessarily adjacent in memory. The advantage of this mode is the ability to spread descriptors. Rabbit 5000 Microprocessor User’s Manual...
Page 241: Circular Queue
21.3.5.4 Circular Queue A circular queue is a buffer array or linked list where the final buffer is linked back to the first buffer in the sequence. This method allows for continuous reception of transfers with- out having to reload the initial address for the DMA buffer descriptor sequence. The “ping-pong buffer,”...
Page 242: Dma With Peripherals
DMA to update the settings of these peripherals at some desired rate. This allows complex PWM waveforms to be generated by using the DMA timed request to update the PWM duty cycles at regular intervals. Rabbit 5000 Microprocessor User’s Manual...
Page 243: Register Descriptions
21.4 Register Descriptions DMA Master Control/Status Register (DMCSR) (Address = 0x0100) Bit(s) Value Description No effect on the corresponding DMA channel. Start (or restart) the corresponding DMA channel using the contents of the DMA (Write- channel registers. This command should only be issued after all the DMA only) channel registers (source, destination, length, and link if applicable) have been loaded.
Page 244 DMA transfers at Priority 2. No DMA transfers while CPU operates at Priority 3. DMA transfers at Priority 3. DMA transfers at any time. DMA interrupts are disabled. DMA interrupts use Interrupt Priority 1. DMA interrupts use Interrupt Priority 2. DMA interrupts use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 245 DMA Master Timing Control Register (DMTCR) (Address = 0x0105) Bit(s) Value Description Fixed DMA channel priority. Higher channel number has higher priority. Rotating DMA channel priority. Priority rotates highest channel number to lowest channel number after every byte is transferred. Rotating DMA channel priority.
Page 246 External DMA Request 0 supplied to DMA Channel 4. External DMA Request 0 supplied to DMA Channel 5. External DMA Request 0 supplied to DMA Channel 6. External DMA Request 0 supplied to DMA Channel 7. Rabbit 5000 Microprocessor User’s Manual...
Page 247 DMA Master Request 1 Control Register (DMR1CR) (Address = 0x0107) Bit(s) Value Description External DMA Request 1 disabled. External DMA Request 1 enabled from Parallel Port D3. External DMA Request 1 enabled from Parallel Port E3. External DMA Request 1 enabled from Parallel Port E7. This bit is reserved and should be written with zero.
Page 248 The eight LSBs of the limit value for the DMA timed request timer are stored. DMA Timed Request Divider High Register (DTRDHR) (Address = 0x0117) Bit(s) Value Description Write The eight MSBs of the limit value for the DMA timed request timer are stored. Rabbit 5000 Microprocessor User’s Manual...
Page 249 DMA y Termination Byte Register (D0TBR) (Address = 0x0108) (D1TBR) (Address = 0x0118) (D2TBR) (Address = 0x0128) (D3TBR) (Address = 0x0138) (D4TBR) (Address = 0x0148) (D5TBR) (Address = 0x0158) (D6TBR) (Address = 0x0168) (D7TBR) (Address = 0x0178) Bit(s) Value Description Byte value that, if matched, will terminate a buffer.
Page 250 (Address = 0x012E) (D3IA2R) (Address = 0x013E) (D4IA2R) (Address = 0x014E) (D5IA2R) (Address = 0x015E) (D6IA2R) (Address = 0x016E) (D7IA2R) (Address = 0x017E) Bit(s) Value Description Bits 23:16 of the initial address are stored in this register. Rabbit 5000 Microprocessor User’s Manual...
Page 251 DMA y Special Control Register (D0SCR) (Address = 0x0180) (D1SCR) (Address = 0x0190) (D2SCR) (Address = 0x01A0) (D3SCR) (Address = 0x01B0) (D4SCR) (Address = 0x01C0) (D5SCR) (Address = 0x01D0) (D6SCR) (Address = 0x01E0) (D7SCR) (Address = 0x01F0) Bit(s) Value Description These bits are reserved and will always be read as zeros.
Page 252 Source address is memory (three-byte) address, auto-increment. Destination address is fixed internal I/O (two-byte) address. Destination address is fixed external I/O (two-byte) address. Destination address is memory (three-byte) address, auto-decrement. Destination address is memory (three-byte) address, auto-increment. Rabbit 5000 Microprocessor User’s Manual...
Page 253 DMA y Length[7:0] Register (D0L0R) (Address = 0x0182) (D1L0R) (Address = 0x0192) (D2L0R) (Address = 0x01A2) (D3L0R) (Address = 0x01B2) (D4L0R) (Address = 0x01C2) (D5L0R) (Address = 0x01D2) (D6L0R) (Address = 0x01E2) (D7L0R) (Address = 0x01F2) Bit(s) Value Description Bits 7:0 of the buffer length value are stored in this register. The DMA does a transfer followed by a decrement of this register, so an initial value of 0x0000 will result in a 65536-byte transfer.
Page 254 (Address = 0x01A6) (D3SA2R) (Address = 0x01B6) (D4SA2R) (Address = 0x01C6) (D5SA2R) (Address = 0x01D6) (D6SA2R) (Address = 0x01E6) (D7SA2R) (Address = 0x01F6) Bit(s) Value Description Bits 23:16 of the source address are stored in this register. Rabbit 5000 Microprocessor User’s Manual...
Page 255 DMA y Destination Addr[7:0] Register (D0DA0R) (Address = 0x0188) (D1DA0R) (Address = 0x0198) (D2DA0R) (Address = 0x01A8) (D3DA0R) (Address = 0x01B8) (D4DA0R) (Address = 0x01C8) (D5DA0R) (Address = 0x01D8) (D6DA0R) (Address = 0x01E8) (D7DA0R) (Address = 0x01F8) Bit(s) Value Description Bits 7:0 of the destination address are stored in this register.
Page 256 (Address = 0x01AE) (D3LA2R) (Address = 0x01BE) (D4LA2R) (Address = 0x01CE) (D5LA2R) (Address = 0x01DE) (D6LA2R) (Address = 0x01EE) (D7LA2R) (Address = 0x01FE) Bit(s) Value Description Bits 23:16 of the link address are stored in this register. Rabbit 5000 Microprocessor User’s Manual...
Page 257: Overview
22. 10/100B -T E THERNET 22.1 Overview Network Port B implements a full 10/100Base-T Ethernet MAC with an industry-standard MII interface for an external PHY chip. The MAC is fully compliant with the IEEE 802.3 Ethernet standard, including support for auto-negotiation, link detection, multicast filtering, and broadcast addresses.
Page 258 The MII interface consists of 20 pins as specified in IEEE 802.3 standard. Two clocks are provided on the interface, one for transmit and one for receive. The two A/D converters and single D/A converter are available for customer use when the Ethernet peripheral is enabled. Rabbit 5000 Microprocessor User’s Manual...
Page 259: Block Diagram
22.1.1 Block Diagram Chapter 22 10/100Base-T Ethernet...
Page 260: Registers
Network Port B Configuration 1 Register NBCF1R 0x0241 00000000 Network Port B Configuration 2 Register NBCF2R 0x0242 00000000 Network Port B Configuration 3 Register NBCF3R 0x0243 00000000 Network Port B Gap 0 Register NBG0R 0x0244 00000000 Rabbit 5000 Microprocessor User’s Manual...
Page 261 Register Name Mnemonic I/O Address Reset Network Port B Gap 2 Register NBG2R 0x0246 00000000 Network Port B Gap 1 Register NBG1R 0x0247 00000000 Network Port B Retransmit Max Register NBRMR 0x0248 00000000 Network Port B Collision Window Register NBCWR 0x0249 00000000 Network Port B Frame Limit LSB Register...
Page 262: Other Registers
RX_CLK and TX_CLK pins. The management data clock on MDC is generated by the Rabbit 5000 by dividing down the peripheral clock as selected in NBMCFR. 22.2.3 Other Registers...
Page 263: Interrupts
22.2.4 Interrupts The network interrupt can be generated by an Ethernet frame being transmitted correctly, transmitted with an error, or if a transmit pause occurs (control frame is transmitted but not the data). The events that generate an interrupt can be selected in NBCSR. The receive frame status is attached to the end of the data frame itself, so the DMA inter- rupt can be used to handle received frame.
Page 264: Receive
4. The packet transmission will proceed automatically when data come in. When the DMA transfer is complete, the DMA interrupt can be used to start the packet processing. The status of the received packet is appended to the received data. Rabbit 5000 Microprocessor User’s Manual...
Page 265: Handling Interrupts
22.3.4 Handling Interrupts The network port transmit interrupt is automatically cleared by reading NBCSR; received packets are handled via the DMA interrupt, which is automatically cleared when the ISR is called. A sample packet transmit interrupt handler is shown below. network_isr:: push af ioi ld a, (NBCSR)
Page 266: Multicast Addressing
0x5F 0x43 0x4D 0x51 0xCD 0xD1 0xDF 0xC3 NBMF2R 0x91 0x8D 0x83 0x9F 0x03 0x1F 0x11 0x0D NBMF1R 0x87 0x9B 0x95 0x89 0x15 0x09 0x07 0x1B NBMF0R 0x49 0x55 0x5B 0x47 0xDB 0xC7 0xC9 0xD5 Rabbit 5000 Microprocessor User’s Manual...
Page 267: Register Descriptions
22.4 Register Descriptions Network Port B Data Register (NBDR) (Address = 0x0200) Bit(s) Value Description Returns the contents of the receive buffer. This register is not normally accessed Read by the processor, but is accessed by the DMA channels. Write Loads the transmit buffer with a data byte for transmission.
Page 268 This bit is reserved and will always read as zero. The Network Port interrupt is disabled. The Network Port uses Interrupt Priority 1. The Network Port uses Interrupt Priority 2. The Network Port uses Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 269 Network Port B Command Register (NBCR) (Address = 0x0206) Bit(s) Value Description No operation. Transmit start command. No operation. Transmit PAUSE control frame command. No operation. Transmit half-duplex backpressure. No operation. Transmit FIFO purge command. These bits are ignored and should always be written as zeros. No operation.
Page 270 Receive frames with broadcast address accepted Receive frames with multicast addresses ignored. Receive frames with multicast addresses accepted if passing hashing filter. Receive frames with mismatched physical addresses are ignored. Receive frames with any physical address accepted. Promiscuous mode. Rabbit 5000 Microprocessor User’s Manual...
Page 271 Network Port B Transmit Extra Status Register (NBTESR) (Address = 0x020C)) Bit(s) Value Description This bit is are reserved and will always be read as zero. No transmit length out-of-range, or not checked. Transmit frame had length out-of-range error. No transmit length check error, or transmit length not checked. Transmit frame had length check error.
Page 272 Controls the state of the MDOEN pin if both network ports are disabled. Write Controls the state of the MDC pin if both network ports are disabled. Read Returns the state of the MDI pin. Rabbit 5000 Microprocessor User’s Manual...
Page 273 Network Port B Configuration 0 Register (NBCF0R) (Address = 0x0240) Bit(s) Value Description These bits are ignored and will always return zeros when read. Disable loopback. Enable loopback. Disable transmit flow control. Enable transmit flow control (PAUSE control frames). Disable receive flow control. Enable receive flow control (PAUSE control frames).
Page 274 Enable immediate retransmit (no back-off). These bits are ignored and will always return zeros when read. Disable preamble length limit checking. Enable preamble length limit checking (12 bytes or less only). Disable preamble checking. Enable preamble checking. Rabbit 5000 Microprocessor User’s Manual...
Page 275 Network Port B Gap 0 Register (NBG0R) (Address = 0x0244) Bit(s) Value Description This bit is ignored and will always return zero when read. Back-to-back interpacket gap. Recommended values are 0x15 for full-duplex operation, and 0x12 for half-duplex operation. These values result in 9.6 µs for 10 Mbits/s and 0.96 µs for 100 Mbits/s, as specified by 802.3.
Page 276 Enable MII scan function. Network Port B MII Reset Register (NBMRR) (Address = 0x0251) Bit(s) Value Description No operation. Reset the MII management module. These bits are ignored and will always return zeros when read. Rabbit 5000 Microprocessor User’s Manual...
Page 277 Network Port B MII Command Register (NBMCR) (Address = 0x0252) Bit(s) Value Description These bits are ignored and will always return zeros when read. No operation. Enable scan. MII module performs continuous read cycles. No operation. Perform one MII read cycle. Network Port B MII Register Address Register (NBMRAR) (Address = 0x0254) Bit(s)
Page 278 (NBSA0R) (Address = 0x0260) (NBSA1R) (Address = 0x0261) (NBSA2R) (Address = 0x0262) (NBSA3R) (Address = 0x0263) (NBSA4R) (Address = 0x0264) (NBSA5R) (Address = 0x0265) Bit(s) Value Description Byte of physical address for transmit control frames. Rabbit 5000 Microprocessor User’s Manual...
Page 279 Enable Network Port Register (ENPR) (Address = 0x0430) Bit(s) Value Description Disable both Network Port B and Network Port C. Enable Network Port B (the 10/100Base-T Ethernet port). Enable Network Port C (the Wi-Fi port). This bit combination is forced whenever either SCFG pin is high.
Page 280 Rabbit 5000 Microprocessor User’s Manual...
Page 281: Chapter 23 802.11B/G Wireless
MAC also performs the CRC check of all received frames and handles the virtual carrier sense functionality. The Rabbit 5000 supports both the infrastructure and the ad-hoc modes. Multicast trans- missions are supported as well. The external interface to the external transceiver consists of 20 digital pins and 8 analog pins.
Page 282: Block Diagram
23.1.1 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 283: Registers
23.1.2 Registers Register Name Mnemonic I/O Address Reset Enable Network Port Register ENPR 0x0430 00000000 Network Port C Version 0 Register NCV0R 0x0A00 00000000 Network Port C Version 1 Register NCV1R 0x0A01 00000001 Network Port C General Control 0 Register NCGC0R 0x0A04 00000000...
Page 284 Network Port C Remaining Backoff 1 Register NCRBO1R 0x0A6B xxxxxxxx Network Port C Beacon Filter Register NCBFR 0x0A6D xxxxxxxx Network Port C Beacon Backoff 0 Register NCBBO0R 0x0A6E xxxxxxxx Network Port C Beacon Backoff 1 Register NCBBO1R 0x0A6F xxxxxxxx Rabbit 5000 Microprocessor User’s Manual...
Page 285: Dependencies
23.2 Dependencies 23.2.1 I/O Pins The wireless network port interface has 28 dedicated pins, as shown in Table 23-1. Of those, 20 are digital and can be used as general-purpose I/O via NBDRR, NBDTR, and NBDMR if the network port is not being used. Table 23-1.
Page 286: Clocks
At the present time, the wireless peripheral is intended to be used only in Rabbit-branded and other products offered by Digi International. The information provided in the Rabbit 5000 Microprocessor User’s Manual should be sufficient to explain the operation of the wireless peripheral in these products.
Page 287: Chapter 24. Input Capture
24. I NPUT APTURE 24.1 Overview The input capture peripheral consists of two channels, each of which contains a 16-bit counter and edge-detection circuitry. The input capture channels are usually used to deter- mine the time between events. An event is signaled by a rising or falling edge (or optionally by either edge) on one of 12 input pins that can be selected as the input for either of the two channels.
Page 288: Block Diagram
Timer B. The minimum time delay needed is probably less than 10 µs if the software is done carefully and the clock speed is reasonably high. 24.1.1 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 289: Registers
24.1.2 Registers Register Name Mnemonic I/O Address Reset Input Capture Ctrl/Status Register ICCSR 0x0056 00000000 Input Capture Control Register ICCR 0x0057 00000000 Input Capture Trigger 1 Register ICT1R 0x0058 00000000 Input Capture Source 1 Register ICS1R 0x0059 xxxxxxxx Input Capture LSB 1 Register ICL1R 0x005A xxxxxxxx...
Page 290: Dependencies
Because of this, there is some delay between the input transition and when an interrupt is requested, as shown below. The status bits in ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR. Rabbit 5000 Microprocessor User’s Manual...
Page 291: Operation
24.3 Operation 24.3.1 Input-Capture Channel The following steps explain how to set up an input-capture channel. 1. Configure Timer A8 via TAT8R to provide the desired input-capture clock. 2. Configure ICTxR to provide the desired start/stop operation and conditions. 3. Configure ICSxR to select the input pins for the start and stop conditions. 4.
Page 292: Capture Mode
5. Reading the latch registers at any time after an initial start pulse is received will return the current count. Until an initial start pulse is received, the latch registers will have a residual value. Rabbit 5000 Microprocessor User’s Manual...
Page 293: Register Descriptions
24.4 Register Descriptions Input Capture Control/Status Register (ICCSR) (Address = 0x0056) Bit(s) Value Description The Input Capture 2 Start condition has not occurred. (Read) The Input Capture 2 Start condition has occurred. The Input Capture 2 Stop condition has not occurred. (Read) The Input Capture 2 Stop condition has occurred.
Page 294 These bits are reserved and should be written with zero. Input Capture interrupts are disabled. Input Capture interrupt use Interrupt Priority 1. Input Capture interrupt use Interrupt Priority 2. Input Capture interrupt use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 295 Input Capture Trigger x Register (ICT1R) (Address = 0x0058) (ICT2R) (Address = 0x005C) Bit(s) Value Description Disable the counter. Applies even in Counter operation. The counter runs from the Start condition until the Stop condition. The counter runs continuously. The counter runs continuously, until the Stop condition. Disable the count latching function.
Page 296 Reading the MSB of the count opens these latches on the MSB of the count. In Counter operation, if no latching condition is specified the value written to this register is returned. Write The eight LSBs of the match value for counter mode are stored. Rabbit 5000 Microprocessor User’s Manual...
Page 297 Input Capture MSB x Register (ICM1R) (Address = 0x005B) (ICM2R) (Address = 0x005F) Bit(s) Value Description The most significant eight bits of the latched Input capture count are returned. In Read Counter operation, if no latching condition is specified the value written to this register is returned.
Page 298 Rabbit 5000 Microprocessor User’s Manual...
Page 299: Overview
ECODER 25.1 Overview The Rabbit 5000 has a two-channel Quadrature Decoder that accepts inputs via specific pins on Parallel Ports D and E. Each channel has two inputs, the in-phase (I) input and the 90 degree or quadrature-phase (Q) input. An 8 or 10-bit up/down counter counts encoder steps in the forward and backward directions, and provides interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00.
Page 300 (0x3FF in 10-bit mode). The timing for the interrupt is shown below. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt and status bits are cleared by reading the QDCSR. Rabbit 5000 Microprocessor User’s Manual...
Page 301: Block Diagram
25.1.1 Block Diagram 25.1.2 Registers Register Name Mnemonic I/O Address Reset Quad Decode Ctrl/Status Register QDCSR 0x0090 xxxxxxxx Quad Decode Control Register QDCR 0x0091 00000000 Quad Decode Count 1 Register QDC1R 0x0094 xxxxxxxx Quad Decode Count 1 High Register QDC1HR 0x0095 xxxxxxxx Quad Decode Count 2 Register...
Page 302: Dependencies
The Quadrature Decoder interrupt vector is in the IIR at offset 0x190. It can be set as Priority 1, 2, or 3. The status bits in the QDCSR are set coincident with the interrupt request and are reset when QDCSR is read. Rabbit 5000 Microprocessor User’s Manual...
Page 303: Operation
25.3 Operation The following steps explain how to set up a Quadrature Decoder channel. 1. Configure Timer A10 via TAT10R to provide the desired Quadrature Decoder clock speed. 2. Configure QDCR to select the input pins for the two channels. 3.
Page 304: Register Descriptions
Quadrature Decoder 1 decremented from zero to the maximum count. This bit is only) cleared by a read of this register. This bit always reads as zero. No effect on the Quadrature Decoder 1. (Write- Reset Quadrature Decoder 1 to all zeros, without causing an interrupt. only) Rabbit 5000 Microprocessor User’s Manual...
Page 305 Quad Decode Control Register (QDCR) (Address = 0x0091) Bit(s) Value Description Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. Quadrature Decoder 2 inputs from Parallel Port D bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2.
Page 306 Rabbit 5000 Microprocessor User’s Manual...
Page 307: Overview
26. P ULSE IDTH ODULATOR 26.1 Overview The Pulse Width Modulator (PWM) consists of a 10-bit free running counter and four width registers. A PWM output consists of a train of periodic pulses within a 1024-count frame with a duty cycle that varies from 1/1024 to 1024/1024. Each PWM output is high for n + 1 counts out of the 1024-clock count cycle, where n is the value held in the width register.
Page 308 Operation in the spread mode reduces the filtering requirements on the PWM output in most cases. The DMA channels on the Rabbit 5000 are designed to work with fixed I/O addresses. To allow DMA control of the PWM, a separate PWM Block Access Register (PWBAR) and PWM Block Pointer Register (PWBPR) are available.
Page 309: Block Diagram
pointer register is initialized to 0x88 (the first PWM register) and the DMA then transfers blocks of eight bytes to completely reprogram the PWM. 0x88 -> 0x89 -> 0x8A -> 0x8B -> 0x8C -> 0x8D -> 0x8E -> 0x8F -> When the DMA destination address is the PWBAR, the DMA request from the PWM is automatically connected to the DMA.
Page 310: Dependencies
The interrupt request is cleared by a write to any PWM register. The PWM interrupt vector is in the IIR at offset 0x170. It can be set as Priority 1, 2, or 3 by writing to PWL0R. Rabbit 5000 Microprocessor User’s Manual...
Page 311: Operation
26.3 Operation The following steps explain how to set up a PWM channel. 1. Configure Timer A9 via TAT9R to provide the desired PWM clock frequency. 2. Configure PWLxR to select whether to spread the PWM output throughout the cycle. 3.
Page 312: Register Descriptions
Suppress PWM interrupts seven out of eight iterations of PWM counter. Suppress PWM interrupts three out of four iterations of PWM counter. Suppress PWM interrupts one out of two iterations of PWM counter. PWM output High for single block. Spread PWM output throughout the cycle. Rabbit 5000 Microprocessor User’s Manual...
Page 313 PWM LSB x Register (PWL2R) (Address = 0x008C) (PWL3R) (Address = 0x008E) Bit(s) Value Description Least significant two bits for the Pulse Width Modulator count. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter.
Page 314 Rabbit 5000 Microprocessor User’s Manual...
Page 315: Overview
ONTROL 27.1 Overview The Rabbit 5000’s external I/O space consists of 64KB that is accessed by prefixing a read or write instruction with the IOE instruction. These accesses can go onto the memory bus or onto the external I/O bus (described below). There are three dedicated signal pins (/IORD, /IOWR, /BUFEN) that toggle for all external I/O accesses, and eight I/O strobes that can be associated with this external I/O space and directed out of Parallel Ports C, D, or E.
Page 316: I/O Strobes
27.1.2 I/O Strobes There are eight I/O strobes available in the Rabbit 5000. Each has a separate 8KB address range that can be enabled as a chip select, read strobe, write strobe, or a read/write strobe. The number of wait states can be set to 1, 3, 7, or 15, and the signal can be active high or low.
Page 317: I/O Handshake
I/O banks. The external device holds this signal (active high or low) when it is busy and cannot accept a transaction. The Rabbit 5000 will then hold midway through the transaction until either the handshake signal goes inactive or a timeout occurs.
Page 318: Block Diagram
IB3CR 0x0083 00000000 I/O Bank 4 Control Register IB4CR 0x0084 00000000 I/O Bank 5 Control Register IB5CR 0x0085 00000000 I/O Bank 6 Control Register IB6CR 0x0086 00000000 I/O Bank 7 Control Register IB7CR 0x0087 00000000 Rabbit 5000 Microprocessor User’s Manual...
Page 319: Dependencies
27.2 Dependencies 27.2.1 I/O Pins The external I/O bus uses PA0–PA7 for data, and either PB2–PB7 or PB0–PB7 for address lines, depending on the setting in SPCR. Address bits 6 and 7 can also be enabled on pins PD1, PD3, PD5, or PD7, which allows PB0 and PB1 to be used as clocked serial I/O instead of as external I/O.
Page 320: Operation
3. Select the handshake timeout value by writing to IHTR. Once enabled, the handshake will be checked for every external I/O transaction in a bank that was enabled in IHSR. After these transactions, the program should check for a time- out by reading IHTR. Rabbit 5000 Microprocessor User’s Manual...
Page 321: Register Descriptions
27.4 Register Descriptions I/O Handshake Control Register (IHCR) (Address = 0x0028) Bit(s) Value Description These bits are reserved and should be written with zeros. I/O handshake is active low (I/O transaction held until signal goes high). I/O handshake is active high (I/O transaction held until signal goes low). This bit is reserved and should be written with zero.
Page 322 Time constant for the I/O handshake timeout counter. This time constant (times 32) selects the number of clocks that the I/O handshake input may delay completion of an I/O transaction before the I/O transaction will complete automatically. Rabbit 5000 Microprocessor User’s Manual...
Page 323 I/O Bank x Control Register (IB0CR) (Address = 0x0080) (IB1CR) (Address = 0x0081) (IB2CR) (Address = 0x0082) (IB3CR) (Address = 0x0083) (IB4CR) (Address = 0x0084) (IB5CR) (Address = 0x0085) (IB6CR) (Address = 0x0086) (IB7CR) (Address = 0x0087) Bit(s) Value Description Fifteen wait states for accesses in this bank.
Page 324 Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus. Slave port interrupts are disabled. Slave port interrupts use Interrupt Priority 1. Slave port interrupts use Interrupt Priority 2. Slave port interrupts use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 325 Parallel Port C Alternate Low Register (PCALR) (Address = 0x0052) Bit(s) Value Description Parallel Port C bit 3 alternate output 0 (TXC). Parallel Port C bit 3 alternate output 1 (I3). Parallel Port C bit 3 alternate output 2 (TIMER C3). Parallel Port C bit 3 alternate output 3 (SCLKD).
Page 326 Parallel Port C bit 4 alternate output 3 (TCLKE). Parallel Port C Function Register (PCFR) (Address = 0x0055) Bit(s) Value Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 10- Rabbit 5000 Microprocessor User’s Manual...
Page 327 Parallel Port D Alternate Low Register (PDALR) (Address = 0x0062) Bit(s) Value Description Parallel Port D bit 3 alternate output 0 (IA7). Parallel Port D bit 3 alternate output 1 (I3). Parallel Port D bit 3 alternate output 2 (TIMER C3). Parallel Port D bit 3 alternate output 3 (SCLKD).
Page 328 Parallel Port D bit 4 alternate output 3 (TCLKE). Parallel Port D Function Register (PDFR) (Address = 0x0065) Bit(s) Value Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 11-1. Rabbit 5000 Microprocessor User’s Manual...
Page 329 Parallel Port E Alternate Low Register (PEALR) (Address = 0x0072) Bit(s) Value Description Parallel Port E bit 3 alternate output 0 (I3). Parallel Port E bit 3 alternate output 1 (A23). Parallel Port E bit 3 alternate output 2 (TIMER C3). Parallel Port E bit 3 alternate output 3 (SCLKD).
Page 330 Parallel Port E bit 4 alternate output 3 (TCLKE). Parallel Port E Function Register (PEFR) (Address = 0x0075) Bit(s) Value Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 12-1. Rabbit 5000 Microprocessor User’s Manual...
Page 331: Overview
REAKPOINTS 28.1 Overview The Rabbit 5000 contains seven hardware breakpoints to support debugging. Each hard- ware breakpoint consists of a 24-bit address match register and a 24-bit mask register. A breakpoint can be generated on an address match for address execution, data read, data write, or any combination thereof.
Page 332: Block Diagram
28.1.1 Block Diagram Rabbit 5000 Microprocessor User’s Manual...
Page 333: Registers
28.1.2 Registers Register Name Mnemonic I/O Address Reset Breakpoint Debug/Control Register BDCR 0x001C 00000000 Breakpoint 0 Control Register B0CR 0x030B 00000000 Breakpoint 1 Control Register B1CR 0x031B 00000000 Breakpoint 2 Control Register B2CR 0x032B 00000000 Breakpoint 3 Control Register B3CR 0x033B 00000000 Breakpoint 4 Control Register...
Page 334: Dependencies
• If single-step functionality is desired, the breakpoint interrupt should be re-enabled by writing the appropriate bit to BDCR. If this is done, the interrupt handler needs to be exited in a particular manner (see below). Rabbit 5000 Microprocessor User’s Manual...
Page 335: Example Isr
28.3.2 Example ISR A sample interrupt handler is shown below. breakpoint_isr:: push af ioi ld a, (BDCR) ; determine which interrupts are pending and ; clear the interrupt request ; handle all breakpoints here ; reenable any breakpoints by writing to BDCR pop af ipres ;...
Page 336: Register Descriptions
Breakpoint x on User Mode write address match. Breakpoint x on System Mode write address match. Breakpoint x on System or User Mode write address match. These bits are reserved and should be written with zeros. Rabbit 5000 Microprocessor User’s Manual...
Page 337 Breakpoint x Address 0 Register (B0A0R) (Address = 0x030C) (B1A0R) (Address = 0x031C) (B2A0R) (Address = 0x032C) (B3A0R) (Address = 0x033C) (B4A0R) (Address = 0x034C) (B5A0R) (Address = 0x036C) (B6A0R) (Address = 0x037C) Bit(s) Value Description Breakpoint x Address [7:0]. Breakpoint x Address 1 Register (B0A1R) (Address = 0x030D)
Page 338 (Address = 0x033A) (B4M2R) (Address = 0x034A) (B5M2R) (Address = 0x036A) (B6M2R) (Address = 0x037A) Bit(s) Value Description Breakpoint x Mask [23:16]. (A one in a bit position inhibits the address compare for that bit position. Rabbit 5000 Microprocessor User’s Manual...
Page 339: Overview
The Rabbit 5000 contains several power-saving features. Since the power consumed by the processor is proportional to the clock speed, the Rabbit 5000 provides 12 clock modes that can go as low as 2 kHz. To further reduce power consumption in those ultra-sleepy modes, various shortened chip select strobes are available to reduce current draw by the attached memory devices.
Page 340: Registers
29.1.1 Registers Register Name Mnemonic I/O Address Reset Global Control/Status Register GCSR 0x0000 11000000 Global Power Save Control Register GPSCR 0x000D 00000000 Global Clock Double Register GCDR 0x000F 00000000 Rabbit 5000 Microprocessor User’s Manual...
Page 341: Operation
29.2.2 Clock Rates The processor and peripheral clocks in the Rabbit 5000 can be run in six different modes using the main oscillator: full speed; divided by 2, 4, 6, or 8; and the processor clock divided by 8 with the peripheral clock at full speed.
Page 342: Short Chip Selects
However, when the processor clock is running off of the 32 kHz clock, it is recommended that the Rabbit 5000 be performing a tight polling loop, waiting for a wake-up event.
Page 343 Chapter 29 Low-Power Operation...
Page 344 32 kHz clock (30.5 microseconds); otherwise the timing is identical to the short chip select options based off the main oscillator. Read strobe figures are shown below. Rabbit 5000 Microprocessor User’s Manual...
Page 345 Chapter 29 Low-Power Operation...
Page 346 Rabbit 5000 Microprocessor User’s Manual...
Page 347: Self-Timed Chip Selects
29.2.4 Self-Timed Chip Selects Self-timed chip selects can be enabled via GPSCR to reduce power consumption even more when running off the 32 kHz oscillator. When self-timed chip selects are enabled, the chip select is only active for a short (selectable) period of time ranging from 110 to 290 ns; this can be enable for both reads and writes, or reads only.
Page 348: Register Descriptions
Processor clock from the fast clock, divided by 6. Peripheral clock from the fast clock, divided by 6. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. Rabbit 5000 Microprocessor User’s Manual...
Page 349 Global Power Save Control Register (GPSCR) (Address = 0x000D) Bit(s) Value Description Self-timed chip selects are disabled. 230 ns self-timed chip selects for read and write. 170 ns self-timed chip selects for read and write. 110 ns self-timed chip selects for read and write. 290 ns self-timed chip selects for read only.
Page 350 20 ns nominal low time. 10001 3 ns nominal low time. 10010 4 ns nominal low time. 10011 5 ns nominal low time. other Any bit combination not listed is reserved and must not be used. Rabbit 5000 Microprocessor User’s Manual...
Page 351: Overview
YSTEM 30.1 Overview The Rabbit 5000 provides support for two tiers of control in the processor: System Mode, which provides full access to all processor resources; and User Mode, a more restricted mode. Table 30-1 describes the essential differences between the System Mode and the User Mode.
Page 352: Registers
0x3E0 00000000 Serial Port D User Enable Register SDUER 0x3F0 00000000 Serial Port E User Enable Register SEUER 0x03C8 00000000 Serial Port F User Enable Register SFUER 0x3D8 00000000 Enable Dual-Mode Register EDMR 0x0420 00000000 Rabbit 5000 Microprocessor User’s Manual...
Page 353: Dependencies
30.2 Dependencies 30.2.1 I/O Pins There are no pin dependencies for the System/User Mode. 30.2.2 Clocks There are no clock dependencies for the System/User Mode. 30.2.3 Other Registers Any writes to the internal I/O registers listed in Table 30-2 are ignored when the System/ User Mode is enabled and the processor is in the User Mode.
Page 354: Interrupts
When the System/User Mode is enabled, it is critical to handle the SU stack in interrupts as well as the IP stack; always perform a SURES before the IPRES at the end of the interrupt. Rabbit 5000 Microprocessor User’s Manual...
Page 355: Operation
The System/User Mode is designed to work with the memory and stack protection features of the Rabbit 5000 processor to provide a seamless framework for protection of critical code. However, there are many levels at which the System/User Mode can be used —...
Page 356: Mixed System/User Mode Operation
If any critical interrupts occur (stack limit violation, system mode violation, write protec- tion violation), System Mode handlers can perform any of a number of operations: restart the application code, signal another device, halt operation, and so on. Rabbit 5000 Microprocessor User’s Manual...
Page 357: Enabling The System/User Mode
Figure 30-3 shows an overview of this level of operation. System Mode User Mode Return from interrupts Interrupt Application handlers code Flash file User-defined system interrupts SYSCALL handler Interrupts, SYSCALL, RST Figure 30-3. System/User Mode Setup for Operating System 30.3.4 Enabling the System/User Mode The following steps describe how to enable the System/User Mode.
Page 358: System/User Mode Instructions
User Mode), or an interrupt occurs, or SYSCALL or RST is executed (to enter System Mode), the current mode is pushed onto the SU register. When a SURES is executed, the previous mode is popped off the SU register. Rabbit 5000 Microprocessor User’s Manual...
Page 359: System Mode Violation Interrupt
The effects of each instruction are: • The SETUSR instruction puts the processor into the User Mode by pushing the correct value into the SU register. • PUSH SU and POP SU push and pop the single-byte SU register on/off the SP stack. •...
Page 360: Handling Interrupts In The System/User Mode
When enabled for User Mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at Priority 2 or 1. INTERRUPT UNDER SYSTEM CONTROL INTERRUPT UNDER USER CONTROL Figure 30-4. Interrupt Handing in the System/User Mode Rabbit 5000 Microprocessor User’s Manual...
Page 361 Some sample code for both System Mode interrupts and User Mode interrupts is shown below. The use of SETUSRP and SETSYSP provides checks against stack mismatches and incorrect System/User Modes coming out of the User Mode handler. systemmode_isr: ; jumped to from interrupt vector table ...
Page 362: Register Descriptions
Bit(s) Value Description Disable User Mode access to Parallel Port B (I/O addresses 0x0040–0x0047). Enable User Mode access to Parallel Port B (I/O addresses 0x0040–0x0047). These bits are reserved and should be written with zeros. Rabbit 5000 Microprocessor User’s Manual...
Page 363 Parallel Port C User Enable Register (PCUER) (Address = 0x0350) Bit(s) Value Description Disable User Mode access to Parallel Port C (I/O addresses 0x0050–0x0055). Enable User Mode access to Parallel Port C (I/O addresses 0x0050–0x0055). These bits are reserved and should be written with zeros. Parallel Port D User Enable Register (PDUER) (Address = 0x0360)
Page 364 Description Disable User Mode access to the Quadrature Decoder (I/O addresses 0x0090– 0x0097). Enable User Mode access to the Quadrature Decoder (I/O addresses 0x0090– 0x0097). These bits are reserved and should be written with zeros. Rabbit 5000 Microprocessor User’s Manual...
Page 365 External Interrupt User Enable Register (IUER) (Address = 0x0398) Bit(s) Value Description These bits are reserved and should be written with zeros. Disable User Mode access to External Interrupt 1 (I/O address 0x0099). Enable User Mode access to External Interrupt 1 (I/O addresses 0x0099). Disable User Mode access to External Interrupt 0 (I/O address 0x0098).
Page 366 Bit(s) Value Description Disable User Mode access to Serial Port D (I/O addresses 0x00F0–0x00F7). Enable User Mode access to Serial Port D (I/O addresses 0x00F0–0x00F7). These bits are reserved and should be written with zeros. Rabbit 5000 Microprocessor User’s Manual...
Page 367 This bit combination is reserved and must not be used. This bit combination is reserved and must not be used. Enhanced (Rabbit 5000) instruction set. These bits are reserved and should be written with zeros. Normal (System Mode only) operation.
Page 368 Rabbit 5000 Microprocessor User’s Manual...
Page 369: Dc Characteristics
31. S PECIFICATIONS 31.1 DC Characteristics Table 31-1. Preliminary DC Electrical Characteristics Parameter Symbol Operating Temperature -40°C 85°C Storage Temperature -55°C 125°C Core Supply Voltage 1.65 V 1.8 V 1.90 V CORE Core Current @ 100 MHz, Wi-Fi enabled, 25°C 194 mA Core Current @ 100 MHz, Wi-Fi disabled, 25°C 32 mA...
Page 370 (rest of device powered) VBATIO 1.65 V 3.3 V 3.6 V (rest of device powered down) 1.65 V 1.8 V 3.6 V VBATIO Current 200 nA (rest of device powered) VBATIO (rest of device powered down) 200 nA Rabbit 5000 Microprocessor User’s Manual...
Page 371: Ac Characteristics
31.2 AC Characteristics Table 31-3. Preliminary AC Electrical Characteristics ± ± ° ° (VDD = 1.8 V 10%, VDD = 3.3 V 10%, T = -40 C to 85 CORE Parameter Symbol Main Clock Frequency on CLKI 100 MHz main Real-Time Clock Frequency on CLK32K 32.768 kHz ±...
Page 372: Memory Access Times
Clock to Memory Write Strobe Delay 3 ns 6 ns High Z to Data Valid Relative to Clock 3 ns 8 ns DVHZ Data Valid to High Z Relative to Clock 3 ns 8 ns DVHZ Rabbit 5000 Microprocessor User’s Manual...
Page 373 Memory Read (no wait states) valid valid Memory Write (no extra wait states) valid valid Figure 31-1. Memory Read and Write Cycles Chapter 31 Specifications...
Page 374 Memory Read (no wait states) valid valid Memory Write (no extra wait states) valid valid Figure 31-2. Memory Read and Write Cycles—Early Output Enable and Write Enable Timing Rabbit 5000 Microprocessor User’s Manual...
Page 375: External I/O Reads
31.3.3 External I/O Reads Table 31-6. Preliminary External I/O Read Time Delays ± ± ° ° (VDD = 1.8 V 10%, VDD = 3.3 V 10%, T = -40 C to 85 CORE Parameter Symbol Clock to Address Delay 4 ns 8 ns Clock to Memory Chip Select Delay 3 ns...
Page 376 External I/O Read (no extra wait states) valid valid valid Figure 31-3. I/O Read Cycles—No Extra Wait States NOTE: /IOCSx can be programmed to be active low (default) or active high. Rabbit 5000 Microprocessor User’s Manual...
Page 377 External I/O Write (no extra wait states) valid valid Figure 31-4. I/O Write Cycles—No Extra Wait States NOTE: /IOCSx can be programmed to be active low (default) or active high. Chapter 31 Specifications...
Page 378: Memory Access Times
C to 85 CORE address bus loading = 60 pF) Clock Clock Doubler Memory Address Memory Output- Period Frequency Nominal Delay Access Enable Access (ns) (MHz) (ns) (ns) (ns) 22.11 29.49 44.24 22.5 33.5 58.98 Rabbit 5000 Microprocessor User’s Manual...
Page 379 All important signals on the Rabbit 5000 are output-synchronized with the internal clock. The internal clock is closely synchronized with the external clock, which is available on the CLK pin. The delay in signal output depends on the capacitive load on the output lines.
Page 380 = T + (min. clock low) - (clock to output enable) - (spreader delay) - (asymmetry delay) - (data setup time) = 34 ns + 12.8 ns - 5 ns - 4.5 ns - 1.4 ns = 36 ns Rabbit 5000 Microprocessor User’s Manual...
Page 381: Clock Speeds
31.4 Clock Speeds 31.4.1 Recommended Clock/Memory Configurations The preferred configuration for a Rabbit-based system is to use an external crystal or reso- nator that has a frequency one-half of the maximum internal clock frequency. The oscillator frequency can be doubled or divided by 2, 4, 6, or 8, giving a variety of operating speeds from the same crystal frequency.
Page 382 70 ns, 0 wait states 70 ns, 1 wait state The Rabbit 5000 is rated for a minimum clock period of 10 ns for both commercial and industrial specifications. The commercial rating calls for a ±5% voltage variation from 3.3 V, and a temperature range from -40 to + 70°C.
Page 383 Table 31-11. Preliminary Maximum Clock Speeds ±10%, Temp. -40°C to +85°C) Industrial Ratings Duty Cycle Minimum Maximum Conditions Requirements Period Frequency (ns) (ns) (MHz) No Doubler or 58.8 Spreader Spreader Only 50.0 Normal Spreader Only 47.6 Strong Doubler Only 1 > (clock low - 52.6 (8 ns delay) clock high) >...
Page 384 50% duty cycle, to obtain the highest clock speeds using the clock doubler you must use an external oscillator buffer that will allow for duty-cycle adjustment by changing the resistance of the power and ground connections as shown below. Figure 31-5. External Oscillator Buffer Rabbit 5000 Microprocessor User’s Manual...
Page 385: Power And Current Consumption
31.5 Power and Current Consumption Various mechanisms contribute to the current consumption of the Rabbit 5000 processor while it is operating, including current that is proportional to the voltage alone (leakage current) and dependent on both voltage and frequency (switching and crossover current).
Page 386: Sleepy Mode Current Consumption
31.5.1 Sleepy Mode Current Consumption The Rabbit 5000 supports designs with very low power consumption by using features such as the ultra-sleepy modes and self-timed chip selects. At the low frequencies possible in the ultra-sleepy modes (as low as 2 kHz), the external memory devices become signifi- cant factors in the current consumption unless one of the short or self-timed chip selects are used.
Page 387: Battery-Backed Clock Current Consumption
31.5.2 Battery-Backed Clock Current Consumption For the battery-backed features of the Rabbit 5000 to perform while the processor is pow- ered down, both the VBAT and VBATIO pins need to be supplied properly. The VBAT pin powers the internal real-time clock and the battery-backed SRAM, while VBATIO powers the /RESET, /CS1, CLK32K, and RESOUT pins.
Page 388 Rabbit 5000 Microprocessor User’s Manual...
Page 389: Ball Grid Array Packages
32. P ACKAGE PECIFICATIONS INOUT 32.1 Ball Grid Array Packages 32.1.1 Pinout 17 × 17 Ethernet Option Figure 32-1. Ethernet Option Pinout Looking Through the Top of Package Chapter 32 Package Specifications and Pinout...
Page 390: Pinout 17 × 17 Wi-Fi Option
32.1.2 Pinout 17 × 17 Wi-Fi Option Figure 32-2. Wi-Fi Option Pinout Looking Through the Top of Package Rabbit 5000 Microprocessor User’s Manual...
Page 391: Mechanical Dimensions And Land Pattern
32.1.3 Mechanical Dimensions and Land Pattern TOP VIEW BOTTOM VIEW Figure 32-3. BGA Package Outline Chapter 32 Package Specifications and Pinout...
Page 392 NSMD Defined Land Diameter 0.406 (0.016) Land to Mask Clearance (min.) 0.076 (0.003) Conductor Width (max.) 0.127 (0.005) Conductor Spacing (typ.) 0.127 (0.005) Via Capture Pad (max.) 0.406 (0.016) Via Drill Size (max.) 0.203 (0.008) Rabbit 5000 Microprocessor User’s Manual...
Page 393: Rabbit Pin Descriptions
32.2 Rabbit Pin Descriptions Table 32-3 lists all the pins on the Rabbit 5000 along with the data direction of the pin, its function, and the pin number on the die. Table 32-3. Rabbit 5000 Pin Descriptions Pin Group Pin Name...
Page 394 Table 32-3. Rabbit 5000 Pin Descriptions (continued) Pin Group Pin Name Direction Function LFBGA Ball MDOEN TXD0 TXD1 Output TXD2 TXD3 TX_EN TX_ER Media-Independent Ethernet Interface (MII) RX_CLK RX_DV RX_ER Input RXD0 RXD1 RXD2 RXD3 TX_CLK MDIO Bidirectional ACT_LED ANT_SEL...
Page 395 Table 32-3. Rabbit 5000 Pin Descriptions (continued) Pin Group Pin Name Direction Function LFBGA Ball VININ VINIP Input Analog Component 0 VINQN — Fast A/D Converter VINQP Clock VOUTNI Analog VOUTPI Output Analog Component 1 VOUTNQ — Fast D/A Converter...
Page 396 Rabbit 5000 Microprocessor User’s Manual...
Page 397: A.1 Alternate Parallel Port Pin Outputs
A. P PPENDIX ARALLEL INS WITH LTERNATE UNCTIONS A.1 Alternate Parallel Port Pin Outputs Table A-1. Alternate Parallel Port A and B Pin Outputs Alternate Output Options External I/O Serial Clock Slave Port PA[7:0] — ID[7:0] SD[7:0] — /SLVATTN — /SCS —...
Page 398 — TIMER C1 RCLKF — TIMER C0 TCLKF — — PWM3 SCLKC — PWM2 — PWM1 RCLKE — PWM0 TCLKE — TIMER C3 SCLKD — TIMER C2 — TIMER C1 RCLKF — TIMER C0 TCLKF Rabbit 5000 Microprocessor User’s Manual...
Page 399: A.2 Alternate Parallel Port Pin Inputs
A.2 Alternate Parallel Port Pin Inputs Table A-3. Alternate Parallel Port Pin Inputs Serial Serial Quad- Input External Hand- Slave Port Ports Ports Network rature Capture Interrupt shake Decoder A–D E–F PA[7:0] — — — — — SD[7:0] — — —...
Page 400 — TCLKE × × DREQ1 — — QRD2A — × — DREQ0 — — QRD2B — SCLKC — × × — INT1 — QRD1A — RCLKF × — — INT0 — QRD1B — SCLKD TCLKF Rabbit 5000 Microprocessor User’s Manual...
Page 401 B.1 Errata The following bugs have been identified in the Rabbit 5000 design, and are present in all devices currently available. All Dynamic C libraries have been corrected these issues, and the compiler correctly generates operational code from C programs as noted below.
Page 402 SRAM. Dynamic C does not generate these instructions from C code, and all instances of them in existing libraries where a potential issue would occur have been Rabbit 5000 Microprocessor User’s Manual...
Page 403 Customers writing assembly code that accesses data in battery-backed mem- ory should avoid using these instructions to do so. Appendix B Rabbit 5000 Errata...
Page 404 Rabbit 5000 Microprocessor User’s Manual...
Page 405 D/A converter clock doubler ....27, 28 Quadrature Decoder ..301 Analog Component 1 Con- clock modes ...... 24 Rabbit 5000 ....... 16 trol Register ....225 clock speeds ....382 reset ........38 Analog Component 1 LSB doubling/dividing ....21 Serial Ports A –...
Page 406 Parallel Port D ....109 MMU ......63 strobes ......316 Parallel Port E ....127 read and write transactions Parallel Port H ....145 priority levels ....81 stack protection ....69 PWM ....307, 310, 311 hardware debugging. stack protection/DMA inter- Rabbit 5000 Microprocessor User’s Manual...
Page 407 action ....401, 402 block diagram ....94 PHDR setup ....143 overview ......57 clocks ........ 94 register descriptions ..146 physical and logical memory dependencies ..... 94 registers ......144 mapping ......59 external I/O bus ....93 peripherals register descriptions ..
Page 408 ICLxR ......296 PBDDR ......95 BxM0R ......338 ICMxR ......297 PBDR ......95 BxM1R ......338 ICSxR ..103, 117, 134, 296 PBUER ......362 BxM2R ......338 ICTxR ......295 PCAHR ....101, 326 DATASEG ....71 ICUER ......363 PCALR ....100, 325 DATASEGH ....71 Rabbit 5000 Microprocessor User’s Manual...
Page 409 PCDCR ....... 101 QDCxR ....... 305 TBSMxR ..... 161 PCDDR ....... 100 QDUER ....... 364 TBUER ....... 365 PCDR ......100 RAMSR ......75 TCBAR ....... 169 PCFR ....101, 326 RTCCR ......52 TCBPR ......170 PCUER ......363 RTCxR ......
Page 410 ...103, 117, 134, 296 Window Register ..275 Register .....254 Input Capture Trigger x Network Port B Command DMA y Source Addr[23:16] Register .....295 Register .....269 Register .....254 low-power operation ..340 Network Port B Configura- Rabbit 5000 Microprocessor User’s Manual...
Page 411 tion 0 Register ..273 Control Register ..270 ter ......114 Network Port B Configura- Network Port B Retransmit Parallel Port D Bit 4 Regis- tion 1 Register ..273 Max Register .... 275 ter ......114 Network Port B Configura- Network Port B Station Ad- Parallel Port D Bit 5 Regis- tion 2 Register ..
Page 412 Serial Port x Long Stop Watchdog Timer Control Global Control/Status Reg- Register .....180 Register .......52 ister ......156 Serial Port x Status Register Watchdog Timer Test Reg- Timer A Control Register .. (asynch mode) ..181 ister ......53 Rabbit 5000 Microprocessor User’s Manual...
Page 413 Timer A Control/Status SMODE pin settings ..41 connections ....207 Register ....154 revision history ....401 master ......207 Timer A Prescale Register master/slave communica- tion ......208 Timer A Time Constant x slave ......207 serial ports Register ....
Page 414 ..Timer B ......157 block diagram ....157 clocks ......158 dependencies ....158 interrupts ....158, 159 example ISR ....159 operation ......159 overview ......157 PWM operation ...157 register descriptions ..160 registers .......158 Timer C ......163 block diagram ....164 Rabbit 5000 Microprocessor User’s Manual...

Digi Rabbit 5000 User Manual

Chapter 1. The Rabbit 5000 Processor

Chapter 2. Clocks

Chapter 10 . Parallel Port C

Chapter 3. Reset and Bootstrap 3.1 Overview

Chapter 11 . Parallel Port D

Chapter 4. System Management 4.1 Overview

Chapter 5. Memory Management

Chapter 13 . Parallel Port H

Chapter 6. Interrupts 6.1 Overview

Chapter 7. External Interrupts

Chapter 8 Parallel Port a

Chapter 18 . Serial Ports E - F

Chapter 19 . Slave Port

Chapter 20 . Analog Components

Chapter 25 . Quadrature Decoder

Chapter 29 . Low-Power Operation

Chapter 23 802.11B/G Wireless

Chapter 30 . System/User Mode

Chapter 24. Input Capture

Chapter 27 . External I/O Control

Chapter 28 . Breakpoints

Chapter 26 . Pulse Width Modulator

I/O Handshake

Chapter 31 . Specifications

Chapter 32 . Package Specifications and Pinout

Appendix A. Parallel Port Pins with Alternate Functions

Quick Links

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