Serial Channel 1, 2 Control Register B - Digi NS7520B-1-C36 Hardware Reference Manual

Serial Channel 1, 2 Control Register B

Address: FFD0 0004 / 44
31 30
RDM1 RDM2
15 14
RTS
TX
Register bit assignment
Bit
D31
D30
D29
D28
D27
D26
Table 88: Serial Channel Control Register B bit definition
29 28 27 26
RDM3 RDM4 RBGT RCGT
13 12 11 10
Reserved TENC
Access Mnemonic
R/W RDM1
R/W RDM2
R/W RDM3
R/W RDM4
R/W RBGT
R/W RCGT
25 24 23 22 21
Reserved MODE
9 8 7 6 5
RDEC
Reset Description
0 Enable receive data match 1/2/3/4
0 When the serial channel is configured to operate in
UART mode, the RDM bits enable the receive data
0
match comparators. A receive data match comparison
0
detection can be used to close the current receive
buffer descriptor. The last byte in the current receive
data buffer contains the match character. Each of
these bits enables the respective byte in the Receive
Match register.
0 Enable receive buffer GAP timer
Detects the maximum allowed time from when the
first byte is placed into the receive data buffer and
when the receive data buffer is closed.
When RBGT is set to 1, the BGAP field in Serial
Channel Status Register A is set when the timeout
value defined in the Receive Buffer GAP Timer
register has expired.
0 Enable receive character GAP timer
Detects the maximum allowed time from when the
last byte is placed into the receive data buffer and
when the receive data buffer us closed.
When RCGT is set to 1, the CGAP field in Serial
Channel Status Register A is set when the timeout
value defined in the Receive Buffer Character Timer
register has expired.
w w w . d i g i e m b e d d e d . c o m
S e r i a l C o n t r o l l e r M o d u l e
20 19 18 17
BIT
Reserved
ORDR
4 3 2 1
Reserved
16
0
2 2 9