Digi NS7520B-1-C36 Hardware Reference Manual page 15

General-purpose I/O pins
– 16 programmable GPIO interface pins
Four pins programmable with level-sensitive interrupt
–
Serial ports
Two fully independent serial ports (UART, SPI)
–
Digital phase lock loop (DPLL) for receive clock extractions
–
32-byte transmit/receive FIFOs
–
Internal programmable bit-rate generators
–
– Bit rates 75–230400 in 16X mode
Bit rates 1200 bps–4 Mbps in 1X mode
–
Flexible baud rate generator, external clock for synchronous operation
–
Receive-side character and buffer gap timers
–
Four receive-side data match detectors
–
Power and operating voltages
500 mW maximum at 55 MHz (all outputs switching)
–
– 418 mW maximum at 46 MHz (all outputs switching)
291 mW maximum at 36 MHz (all outputs switching)
–
3.3 V — I/O
–
1.5 V — Core
–
Integrated 10/100 Ethernet MAC
10/100 Mbps MII-based PHY interface
–
10 Mbps ENDEC interface
–
Support for TP-PMD and fiber-PMD devices
–
Full-duplex and half-duplex modes
–
Optional 4B/5B coding
–
Station, broadcast, and multicast address detection filtering
–
512-byte transmit FIFO, 2 Kbyte receive FIFO
–
– Intelligent receive-side buffer size selection
A b o u t t h e N S 7 5 2 0
w w w . d i g i e m b e d d e d . c o m
3