Interrupt Controller Registers - Digi NS7520B-1-C36 Hardware Reference Manual

Interrupts come from different sources on the chip and are managed with Interrupt
Control registers. Interrupts can be enabled/disabled on a per-source basis using the
Interrupt Enable registers. These registers serve as masks for the different interrupt
sources.

Interrupt controller registers

Address: FFB0 0030 / 0034 / 0038
There are five pairs of registers in the interrupt controller:
Interrupt Enable register. A read/write location for reading and writing all
interrupt enable bits as a typical register.
Interrupt Enable Set/Interrupt Status Enabled registers. Perform two
different functions depending on whether a register is read or written:
–
–
Interrupt Enable Clear/Interrupt Status Raw registers. Perform two
different functions depending on whether a register is read or written:
–
–
31 30
15 14
SER SER
1 RX 1 TX
Register bit assignment
All registers use the same 32-bit layout.
When read, the register indicates the current state of all enabled
interrupts.
When written, a 1 in a bit position sets that interrupt enable; a 0 in a bit
position has no effect.
When read, the register indicates the current state of all interrupts
regardless of the state of the enables.
When written, a 1 in a bit position clears that interrupt enable; a 0 in a bit
position has no effect.
29 28 27 26
DMA1-13
13 12 11 10
SER SER
Reserved
2 RX 2 TX
25 24 23 22 21
9 8 7 6 5
Watch Timer
MAC1
Dog 1
w w w . d i g i e m b e d d e d . c o m
G E N M o d u l e
20 19 18 17 16
ENET ENET
Rsvd
1 RX 1 TX
4 3 2 1 0
Timer PORT PORT PORT PORT
2 C3 C2 C1 C0
8 1