Oscillator Characteristics - Digi NS7520B-1-C36 Hardware Reference Manual

Signal
BCLK
A[27:0], TS_, TA_, TEA_, BR_, BG_, BUSY_, DATA[31:0]
BE[3:0]
CS[4:0]_, CAS[3:0], RW_, WE_, OE_
MDC, TXD[3:0], TXER, TXEN, TDO
Table 101: Output buffer derating by load capacitance

Oscillator Characteristics

Figure 31 illustrates the recommended oscillator circuit details.
Rise/fall time. The max rise/fall time on the system clock input pin is 1.5ns
when used with an external oscillator.
Duty cycle. The duty cycle is system-dependent with an external oscillator.
It affects the setup and hold times of signals that change in the falling clock
edges, such as WE_/OE_.
Recommendation: Use a 3.3V, 50±10% duty cycle oscillator with a 100 ohm
series resistor at the output. The PLLs can handle a 25% duty cycle clock
(minimum high/low time 4.5nS).
E l e c t r i c a l C h a r a c t e r i s t i c s
Derating (ns/pF)
0.069
0.150
0.300
0.137
0.274
w w w . d i g i e m b e d d e d . c o m
2 6 3