Digi NS7520B-1-C36 Hardware Reference Manual page 103

Bits Access Mnemonic
D20 R/W AMUX
D19 R/W A[27]
D18 R/W A[26]
D17 R/W A25
Table 36: MMCR bit definition
M e m o r y C o n t r o l l e r M o d u l e
Reset Description
0 Enable external address multiplexing
0 Disable external address multiplexing on
PORTA2 for all DRAM banks
1 Enable external address multiplexing on
PORTA2 for all DRAM banks
Controls whether the NS7520 uses its internal
DRAM address multiplexer.
When set to 0, the NS7520 uses the internal DRAM
address multiplexer for all DRAM access cycles.
The DRAM RAS/CAS multiplexed address is
routed through the A13:A0 pins. See "NS7520
DRAM address multiplexing" on page 105 for more
information.
When set to 1, the NS7520 uses an external DRAM
multiplexer. The RAS/CAS address select signal is
routed out the PORTA2 signal. The external DRAM
RAS/CAS multiplexer uses the PORTA2 signals to
determine when to switch the address multiplexer
0 Enable A27 output
0 CS0OE_ is driven out the A27 pin
1 The A27 signal is driven out the A27 pin
The bit settings determine how the NS7520 uses this
signal. See "A27 and A26 bit settings" on page 92
for more information.
0 Enable A26 output
0 CS0WE_ is driven out the A26 pin
1 The A26 signal is driven out the A26 pin.
The bit settings determine how the NS7520 uses this
signal. See "A27 and A26 bit settings" on page 92
for more information.
1 Enable A25 output
Always set to 0; used for address bit 25.
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