Digi NS7520B-1-C36 Hardware Reference Manual page 255

Bits Access Mnemonic
D28 R/W TXSRC
D27 R/W RXEXT
D26 R/W TXEXT
D25:24 R/W CLKMUX
Table 90: Serial Channel Bit-Rate register bit definition
Reset Description
0 Transmit clock source
0 Internal
1 External (input through OUT2 signal)
Controls the source of the transmitter clock. The
transmitter clock can be provided by an internal
source, as determined by the value in the TICS field,
or by an input on the OUT2 signal attached to the
PORTC pin (configured as a special function input).
0 Drive receive clock external
0 Disable
1 Enable; drive RXCLK out OUT1 signal at
PORTA/PORTC
Enables the receiver clock to be driven on the OUT1
signal attached to the PORTA/PORTC ports. When
using the OUT1 signal, the PORTA/PORTC pin must
be configured as special function output.
0 Drive transmit clock external
0 Disable
1 Enable; drive TXCLK out OUT2 signal at
PORTC
Enables the transmitter clock to be driven on the
OUT2 signal attached to PORTC port. When using
the OUT2 signal, The PORTC pin must be configured
as special function output.
0 BRG input clock
00 Input clock defined by F
01 Input clock defined by F
10 Input clock defined by input on OUT1
11 Input clock defined by input on OUT2
Controls the bit-rate generator clock source. The bit-
rate generator can use one of four clock source: the
external oscillator, the internal PLL SYSCLK output,
an input signal on the OUT1 signal on PORTA/
PORTC, or an input signal on the OUT2 signal
attached to PORTC.
When using either OUT1 or OUT2, the PORTA/
PORTC port pin must be configured as special
function input.
w w w . d i g i e m b e d d e d . c o m
S e r i a l C o n t r o l l e r M o d u l e
XTALE
SYSCLK
2 4 3