Gen Module Registers; System Control Register - Digi NS7520B-1-C36 Hardware Reference Manual

GEN module registers

All registers are 32 bits unless otherwise noted.

System Control register

Address: FFB0 0000
General information
All bits in the System Control register are active high unless an underscore (_)
appears in the signal name; the underscore indicates active low.
31 30
LEND-
IAN
15 14
USER BUSER
Register bit assignment
Bits
D31
D30:29
D28
D27:25
Table 24: System Control register bit definition
29 28 27 26
Reserved
BCLKD Reserved
13 12 11 10
DMA TEA MIS
Rsvd
TST LAST ALIGN
Access Mnemonic
R/W LENDIAN
N/A Reserved
R/W BCLKD
N/A Reserved
25 24 23 22
SWE SWRI
9 8 7 6
CPU DMA
Reserved
DIS RST
Reset Description
Configure chip to run in Little Endian mode
ADDR27
Controls the Endian configuration for the NS7520.
1 Configures the chip to operate in Little Endian mode
0 Configures the chip for Big Endian mode
N/A Initialized to and always read as 10 (full speed).
0 BCLK output disable
0 BCLK output enabled
1 BCLK output forced to LOW state
Shuts down the operation of the BCLK signal. Turning off
the BCLK signal minimizes electro-magnetic interference
(EMI) when BCLK is not required for an application.
N/A N/A
w w w . d i g i e m b e d d e d . c o m
G E N M o d u l e
21 20 19 18 17
SWT N/A BME
5 4 3 2 1
BSYNC Reserved
16
BMT
0
6 3